HP 3562A Service Manual page 297

C I RC U IT D E SCR I PT I O N S
SYSTEM A D D R E S S B U S B U F F E R
T h e system add ress bus buffer (U505) appears as a read-o n l y port to the TMS320 syste m .
T h i s register is used to te l l the TMS320 processor which port the system C P U wants to
a c cess on the FFT board. These ports exists as RAM registers i n s i d e the TMS320.
SYSTEM DATA BUS I N T E RFAC E
T h e system data i nterface (U 506-U509) appears as one read-only register and one w rite­
o n ly register to the TMS320 system. E ach is activated by the FF port decoder. These registers
a re used to transfer data between the FFT board and the system C P U (A2).
F FT I N T E R R U PT
T h e FFT board is contro l led and mon itored by the system C P U throu gh the use of pseudo­
registers i nside the TMS320 i ntegrated c i rcu it. When the system CPU execu tes a wri te or
read to one of these ports, the interru pt c i rc u i t on the FFT board generates an i nte rru pt
s ignal w h i c h is sent to the TMS320 .
T h e FFT i nterru pt c i rc u it cons ists of an ide ntity comparato r con nected d i rectly to the i n­
c o m i n g system address bus. When the system C P U add resses the FFT board, the ide ntity
com parator (U51 0) i n the interru pt block activates the BRDS E L H (board se lect, active hi gh)
w h ich gene rates an i nterru pt for the TMS320.
To determ ine which (pseudo) register the system CPU is req uesting access to, the FFT inter­
r u pt service routine reads the add ress b u s (th rough the address bus buffer, U505) onto
the i nternal data bus. When the add ress is read, the i nte rru pt is cl eared and the data is
transferred i n the appropriate d i rection throu gh the system data bus.
I f the CPU is writi ng to the FFT board , the TMS320 reads the data registers by asse rti ng
the S D B U S I N L (system data bus in) s i gnal w h i c h activates DTAC K L (data acknow l edge).
W hen the system CPU receives the DT AC K L s ig n a l , it rem oves (or changes) the ad d ress,
which deactivates BRDSE LH, which deactivates DT ACKL. I f the FFT is writi ng to the C P U ,
t h e FFT puts the data on the output data iegisteiS ( a wiite operation) and perfo r m s a
(d u m my) read to activate DTAC KL, te l l i n g the C P U that the data on the bus is val i d . W h e n
the CPU f i n ishes read i ng the data it r�mo\les the FF T Ciqd ress, which deactivates B R D S E lH,
C P U I N T E R R U PT
T h e CPU i nte rru pt c i rcu it cons ists of an R-S f l i p-f lop with two Reset i n puts and o n e Set
i n put. I nverters are used i n pairs to e n s u re a single TT L load on the system bus. The R E S E T L
s i gnal from the system resets the C P U i nte rrupt c i rc u it to e n s u re that the FFT board does
not have an i m pend i n g i nterru pt requ est afte r a reset.
T h e FFT performs a CPU interrupt by activating the SI RQSYS L (set i nterru pt request, system)
l i ne w h i c h activates I RQT4 L on the system bus. When the system C P U ru n s its i nte r r u pt
s e rvice routine, it reads the status register on the FFT board and the TMS320 resets the
i nterru pt.
6-78
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MOD E L 3562A
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