HP 3562A Service Manual page 512

S E RV I C E
B. Signal Verification
Verify the fol l ow i n g signals and supply voltages:
1 . Check the + 5V level at A S TP5 and the + 8V level at AS U1 01 -7 and AS U1
2 . The phase c l ocks for channel 1 and channel 2 and the i r test locations are:
CH1 4>1 AS TP1
CH1 4>2 AS TP2
CH 24>1 AS TP3
CH 24>2 AS T P4
Com pare the ph ase cl ocks as fol lows:
a. The two c l ocks for each channel should vary between 0 and + 8V and shou ld
be 90° out of phase. See waveform #1 , tab le A5-1 .
b. Phase clock CH1 4>1 should be in phase with CH24>1 . See waveform #2, table 1\5-1 .
c . Phase c l ock C H 1 4>2 shou ld be i n phase with CH 24>2 .
3 . Ver ify the signals CH1 S H I FT1 (AS U401 -1 9) and CH2SH I FT1 (AS U41 5-1 9). (See
waveform #3, table A5-1 ). If each of these signals is a 200 ns p u l se at a 256 kHz
rate, then the channel 1 and channel 2 d igital fi lters are accepting data. If the
d igital fi lters are not accepti ng data, the pu lses occ u r at a 51 2 k H z rate.
4. Verify the SYNC2 s ignal at AS U401 -20 and AS U41 5-20 (waveform #4, tab le A5-1 ).
The SYN C2 signals are only active when the digital fi lter has accepted a data point.
5. Verify the fol lowi ng bus requests from the fi lter controls (see waveform #5, tab le
A5-1 ):
C H1 BR2 AS U401 -47
CH1 BR3 AS U401 -34
C H 2 BR2 AS U41 5-47
CH2 BR3 AS U41 5-34
If these signals are correct, the f i l ters are ask i n g for the bus.
6. Verify that the MCLK signal (AS TP20) is changing between TTL levels. This indicates
that channel 1 and channel 2 d igital fi lter c i rcu its are being synchronized.
7 . Verify that s i g n a l CH1 1 0 E N is co rrect (waveform #6, table A5-1 ). Verify that s ignal
C H 2 1 0 E N is a s i m i l ar but non-pe riod i c p u l se.
8. Verify that signal I RQT5 L (A6 U401 -6) is changing between TTL levels. This indic . a tes
that the i nterrupt c i rc u its are pas s i n g d ata.
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MO D E L 3 562A
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4-7.