HP 3562A Service Manual page 287

MO D E L 3S62A
6-9 AS, GLOBAL RAM/DISPLA Y CONTROL
A 1 7, DISPLAY INTERfACE
The global RAM board stores data and arbitrates access to memory. It also works with
the d i s p l ay i nterface board to control the transfer of data from mem ory to the d i s p l ay.
Refer to the b lock d i agrams in figures 6-A8a and 6-A8 b and the schematic in figu res 9-A8a
and 9-A8b as referenced in the fo l low ing c i rc u it descriptions.
Arbiter
The arb iter section controls access to g lobal RAM. Seven devices send memo ry req uest
s i g n a l s to the arbiter. The sync h roniz ing register (U 507) syn c h ronizes the s i g n a l s com i ng
o nto the board with respect to the' global RAM . The priority decoder (US06) samp les the
m emory req uests period ically and a l locates mem ory cyc les based on the fol lowing priority
l ist:
1 . FFT, A9
2 . D F1 (Digital Fi l ter Channel 1 ), AS
3 . D F2 (Digita l F i l ter Channel 2), AS
4 . R F S H (Mem ory Refresh), A8
5 . B2 D2 (Displ ay I nterface), A1 7
6. FPP, A7
7. 68 (System CP U), A2
8 . I d l e (If n o device has asserted a memory req uest, the memory/global b u s
transce ivers are d isab led to p revent memory access.)
The feedback network (U40S, U407, U408, and U S08) prevents any device f rom rece iving
two consec utive m e m o ry cyc les. The o n ly exception i s the FPP, which i s a l l owed two
consecutive memory cycles if no h i gher priority device i s requesting memory.
A two-wi re handshake coord i nates memory req uests and g rants. When a device wants
m e mory access, it f i rst sets up val id global add ress and data at its output bus d rivers.
T he device then i n itiates handshak ing by asserti ng its memory request l i ne l ow. When
the device is ai located a memory cyc le, its mem ory g rant line goes l ow. This signal enables
the devi ce's add ress and data bus drivers. The add ress flows to the gl obal RAM add ress
...... . .. ' � ..
Global Timing
The gl obal t i m i n g section cons ists of a d e l ay l i ne osc i l l ator and gating logic. T h ree d e l ay
l in es (U31 1 , U31 2, and U41 1 ) each have ten taps, eac h tap delayed 1 0 n s from the previous
tap. The output from the th i rd tap of the th i rd del ay l i ne feeds back through an i n ve rter
to the i n put of the fi rst delay l i ne. The pol arity of the s ignal cha nges every 235 nsec
(230 nsec through the delay l ines p l u s S nsec through the inverter). The res u lt is a 2.1 3
M H z square wave. This signal is tapped at several intervals along the delay l ines and passed
t h rough com b i n ations of logic gates to generate t i m i ng s ig n a l s .
C I RC U IT D E SC R I PT I O N S
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