HP 3562A Service Manual page 328

LOCK DETECT
Error
PHASE
DETECTOR
Voltage
80
kHz
80 kHz
BAN DPASS
F I LT E R
Difference
Frequencies
SAMPLER
b
Figure 6-A3 1 Trigger
AND
SPEED U P
PLL GAIN Control
AND VCXO
Voltage
SHAPING
,
20.48
+ 6
MHz
,
Clock Block
Diagram
,
+ 2
+ 4
+ 1 0
SE LXS
+ 1 0
CONVERT
20.48
MHz
10.24
MHz
SMPOUT
To Power
Supply
1 External Sample
nternal Sample
=
=
o
I
CONV
M U LTI- TO ADC
PLEXER
6-1 1 1 /6-1 1 2