HP 3562A Service Manual page 271

C I RC U I T D E S C R I PT I O N S
T h e local data/DMA bus i nterface (AS U406 and ASU41 1 ) latches start and stop ad d resses
onto the DMA bus. This i nformation is u sed by the DMA controll er(s) to partition the global
RAM on AB for the d iff erent output modes of the DMA contro l le r.
T h e global data bus i nterface (AS U304 and AS U404 for the channel one d i g ital f i lter and
A S U 31 3, AS U41 3 for the channel two d igital f i lter) latches data f rom the digital f i lter data
b u sses to the global data bus.
T h e global b u s D M A control c i rc u it takes the decoded ad d ress i nfo rmation f rom the DMA
a d d ress decod ing f u nctional b l o c k . The decoded i nformation programs this b l ock i nto
the correct state m a c h i ne mode for the output f rom the d igital f i lters. The contro l l i ne
outputs f rom this f u n ctional b l ock co ntrol the ti m i ng and syn c h ro n i z ation of the output
b uff ers and AB global RAM addres s i n g .
T h e parallel input contro l c i rc u it co ntrols the transfer of para l l e l data f rom the global
RAM i nto the d igital f i lters through the gl obal data bus interf ace.
A6,
Digital Filter Controller Block Descriptions
Refer to f igure 6-ASd, A6 Bl ock D iagram, for the f o l lowing c i rc u it block desc riptions.
SYSTEM DATA BUS I NTE RFAC E
T h e system data bus i nterf ace consists of tristate transceivers connecti ng the system d ata
b u s and the local data bus. The system C P U conf igu res and reads status f rom various
registers in the d ig ital f i lter asse m b l y through this i nterf ace and the local d ata b u s .
SYST E M A D D R E S S D E COD E R
T h e system add ress decoder i s d ivided between the AS and A6 boards with some of the
c ircu itry appearing on each . The system address bus is connected to the A6 control board .
Part of the add ress (AS L-AB L and VI OL) i s decoded by the system add ress decoder (A6U404).
T h is IC is an eight-b it ide ntity comparator conf igu red to activate the signal MYA D D RS L
when the f iiter assem biy is add ressed by the system C P U .
d ecoders on the control (A6) and f i l te r boards A(S).
T h e add ress decoder on the co ntrol board (A6U 304) decodes add ress i nfo rmation i nto
meas u rement com mands, counting i nstru ctions, and i nterrupt m asks.
D ATA PO I NT C O U NT E R
T h e d ata point cou nter mon itors the i nformati on req u i red to syn c h ro n i ze the actio n s of
the various components of the f i lter assembly. A6U1 09 contains f ive 1 6-bit cou nters u sed
to cou nt th e nu mber of data poi nts (sam p les) stored in G l obal RAM. Conf igu ration
i nformation f rom the system CPU is written i nto this cou nter and status i nf o rmation read
f rom it via the local data bus. E ach of the f ive cou nters has an output (OUT1 through
OUTS) to si gnal when the cou nter h as reached its term i n a l cou nt.
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MO D E L 3S62A