HP 3562A Service Manual page 285

)
)
To A2 System CPU
I RQT3L
To A2 System CPU
System
System
Address
Address Decoder
and
Bus
Handshake
From
System CPU
A1 L to A8L
System Command
Pointer
Data
Registers
Bus
From
System CPU
DOL to D1 5 L
8 MHz ,.
Clock
Generator
SYSCLK
From
MHz
4
System
CPU
CCODE
ADDFLG
Condition
Code
Multi­
Plexer
TB I T
I nstru ction
Matching
PROM
Data Block Address ..
8-23
..
B Bus 0-23
MRFLG
X
Bus 8-23
Condition
Pipeli
'Code
Sequen
(AM 291
Pipel ine D.B. 0-7
Arithmetic
Logic U nits (ALU's)
(AM 2903)