A33, A35 Input - HP 3562A Service Manual

MOD E L 3562A
6-16 A33, A3 5 INPUT
T he i n p u t assembly (along with the ADC) i m p l em ents the voltage , ranges and cond itions
the i n pu t s i gnals. The i n put overl oad detect c i rc u i t warns the operator that the reference
voltage is excessively high. The common mode rejection DAC compensates for differences
between the H I G H i nput and the LOW i n put c i rc u its.
The block d iagram of the i n p u t asse m b ly is shown in f i g u re 6-A33. The HP 3562A has two
channels of bal anced d iffere ntia l i n puts; the A33 I n put assembly is identical to the A35
I n put assem bly. E ach asse m b l y has a H I G H i n p u t and a LOW inpu t. The H I G H input i s
the chan nel's B N C center conductor and the LOW i n pu t is the channel's B N C she l l
condu ctor. The H I G H and LOW i n p u t signals are attenuated by a l adder attenuators. The
i n put attenuators u se res istors for low frequency attenuation and adj u stab le capacitors
for high freq uency flatness response. An internal analog s ignal (ST I M @ ) from the A30
Analog Source assem bly is put i nto the H I G H s ignal path. The i nstrum ent uses t h i s s i g n a l
f o r self-tests a n d c a l i bration.
After the s ignal is atte nuated , it goes into a buffer. The buffer's power s u p p l ies are
bootstrapped to al l ow for a 20V common mode signal. After the H I G H i n put and LOW
in put s ignals are attenuated and buffered, they are su btracted using a d ifference a m p l ifier.
'The output of the d i fference a m p l ifier is sent to a times three ampl ifier which is adj ustab le
for gain and de offset.
After the d ifference ampl ifier, th ree attenuator/gain stages p rov ide the 2 d B inte rmed i ate
gain and atte n u ation steps. One of the stages is on the i n put assem bly and the other t wo
stages are on the ADC assem b ly. E ach stage contains a m u lt i p l exer and a times three
a m p l ifier.
The in put assem bly is control led by two serial-in para l l e l-ou t sh ift registers and rel ay d rive
c i rcu its. The serial control data word (C NTLD) from the A1 Di gital Source is s h ifted into
the registers and then the output is latched by the load channel signal (LDCH L). This control
word determ i nes w h i c h of the re l ays are set, the settings f o r the m u lt i p l exers in the
attenuator/gain stages, the common mode rejection DAC output val ue, and the de offset
value (ci rcuit on the ADC assemb ly). T he input sends the ADC its control data word (CNTLD
AD) from the inte rface sh ift registers.
C I RC U I T D E SC R I PT I O N S
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