HP 3562A Service Manual page 262

C I RC U I T D E SC R I PT I O N S
The AS D igital Fi lter sends the SYNC2 s ignal to the LO when it is ready for the next s i ne
a n d cosine wave data po i nts. The data poi nts are sync h ro n i z ed with SYNC2 and shifted
o u t to the d igita l fi lter and d i gital sou rce. Each serial data stream rep resents one po i nt
(ampl itud� val ue) on a s i n e o r cos i n e wave.
E ach samp l e pe riod co rresponds , to an LO° ' c s u per-cy c l e'. E ach super-cycle is com posed
of four cyc les defined by the state variables SO and 51 . The phase accu m u l ato r generates
a p hase v a l u e for si ne, cos i ne, or sou rce d u ri n g each cyc le except for one w h i c h is u sed
f o r general housekeep i n g . T h i s i s shown below:
51 (U 46-5)
o
o
1
SYNC2 occu rs
1
W h i le the present phase val ues are being generated i n the phase acc u m u l ator, the previous
set of data poi nts are being p rocessed in the i nterpo lator and adder, and the set of data
po i nts before that are bei n g sent to the d igital f i l ter and d igital source. So, at any given
time, there are a cou ple of sets of data points in process . T h e pro cess repeats u nt i l the
LO operation is cha nged by the system C P U .
W hen a trigger occu rs, t h e phase va l u e of t h e cos i n e is l atched i nto t h e phase output
l atchs. The system CPU reads this va l u e through the system bus i nterface and uses this
i nformation for an i n put co rrection factor. The self-test sh ift registers are u sed to test the
assem bly. D u ring self-test, the system CPU reads and verif ie ' s the val u es from the self-test
s h ift reg isters and the phase l atchs.
System Bus 'nteifaCe
A l l com m u n ications between the
from the system C P U . To send a com m and or data to the LO, the system CPU puts the
c om mand or data on the system data b u s (00 to 07) and add resses the LO. A comparator
( U 3 7) checks A4 L to A8L, L D S L, ASl, and V I O L for a val id add ress. When the add ress is
v a l id, the comp arator asserts the Val id Add ress l i ne (VAOO R) w h i c h enab les the syste m
b u s PA L . The PAL sets the Va l i d Perip heral Address l i n e (VPA L) low to e n a b l e the system'
d ata bus b uffers (U24, U28) and to handsh ake with the system C P U . When the system
C P U receives VPAL, it sync h ro n i zes the Val id Mem ory Address l i ne (VMAL) with the
E nable C l ock (E N B L L). The data is transferred w h i l e VMA L is l ow. System bus l i nes are
o n l y val id as long as VMA L i s l ow.
6-40
so
(U46-9) Output of Phase Accu m u l ator
o
C os i n e data po i nt
1
No output, set up for next su per-cyc le
1 S i n e d ata point
o
N DAT data po i nt
MO D E L 3S62A