HP 3562A Service Manual page 249

MOD E L 3562A
Refer to Figure 6-A2 for this discussion. The processing unit of the A2 System C PU (Central
6-4 A2 SYSTEM CPU/HP'S
Processing U n it) is a MC68000 1 6-bit m icro processor. The fu nction of the system C P U i s
to tel l each assembly which process to execute and mon itor the overall fu nction i ng and
data processing of the instrument. The programs stored in memory (monitor memory) on
the A2 System CPU and some of the programs on the A3 program ROM help the system
CPU perform this function. The monitor memory is made up of ROM, RAM, and nonvolatile
RAM (which is maintained by a battery backu p).
The H P-I B interface is incl uded on the A2 CPU assemb ly. This allows for d i rect memory
access and a H P-I B device to talk d i rectly with the system processor.
The system CPU is the system add ress and data bus master of all com munications on
the system bus. I nteractions between the assem bl ies are maintained by using 1 6
bidirectional data lines (DOL to D1 5L), 23 address lines (A1 L to A23L), and 1 7 system control
l i nes. An assembly attracts the attention of the A2 System CPU by using interrupt l ines
I RQT2 L to I RQT6L. The priority i nterrupt encoder determ ines when an assem bly can
interrupt the system processor. When interru pted, the system CPU processes the interrupt
and sends the next command to the assembly. After receiving the information, the assembly
handshakes with the system C PU . Most assemb l ies use the asynchronous signal Data
Transfer Acknowledge (DTACKL) to handshake with the system CPU. The exception is the
A4 Local Oscil lator. It uses the synchronous signal Valid Peripheral Add ress (VPAL) to
handshake with the system CPU.
The system processor uses the system bus control, system add ress drivers, system data
Off-Board Operations
buffers, and handshake circu its to get programs stored i n the A3 P rogram ROM and to
command assem bl ies to perform operations. When the system C PU needs to load an
instruction, it asserts the read/write l ine (WR I TE L) low and puts the add ress for the
A3 ROM assembly and the address of the needed instruction on the syste m address bus.
The A3 ROM decodes the add ress l i nes, retu rns the DT ACKL to the system CPU, and puts
the requested instruction on the system data bus. The system CPU then loads the instruc­
tion from the system data bus.
1 . The system processor puts the address for the assem b ly on the system add ress b u s
and the add ress decoder activates the proper control l ines.
2. The add ress decoder selects the appropriate mon itor memory location where the
command is stored and the command is put on the system data bus:
(To command the A7 Floating Point Processor, the system C PU loads a command stack
i nto the A8 G l obal RAM before addressing the assembly. The data transferred on the
system data bus is the starting address of the command stack in global RAM.)
3. The assembly recognizes it has been addressed and returns a handshake signal (DT ACKL
or VPAL).
C I RC U I T D E SC R I PT I O N S
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