HP 3562A Service Manual page 295

C I RC U I T D E SC RI PT I O N S
Address Generation
T h e FFT board must c reate add resses for the data i n put from and output to RAM when
it has control of the gl obal bus. T h i s f u n ction i s a major portion of the activity on t h e
FFT board. The b lock entitled Add ress G e n e ration on the m a i n block d i agram has its own
b l ock d iagram made up of the blocks l isted as follows. Refer to figure 6-A9b for the fo l low­
i n g d iscussion.
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I/O Sequencer
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Sequence Decoder
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Cou nters One and Two
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Add ress Tran s l ator
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Page Registe r
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Coefficient ROM
I /O S E Q U E NC E R
T h e I/O sequencer (U1 1 7) co ntro l s the I /O process when the FFT board h as control of the
g l obal bus. It manages the timing for gl obal bus I/O and di rects the generation of add resses
used to transfer data to and from global RAM. The TMS320 syste m co ntro l s the I/O
s e q u e n cer through the hardware control register. The sequencer is syn chron ized to the
TMS320 operations through the port decoder to te l l the sequencer when the TMS320 has
ac cessed or provided data for the next I/O operation. The sequencer also i n iti ates hand­
s h ak i n g when the FFT needs memory access.
S E Q U E NC E D ECOD E R
T h e sequ ence decoder (U1 1 5) decodes the outputs of the I/O sequencer. When the TMS320
b e g i n s a new level (the Fast Fourier Transform is performed in " l evel s", five of w h i c h are
c a l led "butterfly routines") it i n itial izes the sequencer by activating LDHWCRL (load hard­
ware control register). T h i s s ignal from the port decoder also presets the seq uencer (U 1 1 7),
starti ng the sequencer process. The mem ory access process is as fo l l ows:
e
The sequencer asserts R E Q G B L (req uest global bus) to the global b u s handshaking
c i rcu itry which produ ces a mem ory req uest (M RFFT L) to global RAM .
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I f it's a read operation the read regi sters get l oaded by G D S L (global d ata strobe). I f
it's a write operation, the write regi sters o n the g lobal data b u s are e n ab led and the
G R/G WL (g lobal read/global wr ite) signal is set low.
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When global RAM rem oves the m e m o ry grant signal (s ignal ing that the cyc le i s com­
pl ete) the add ress, data, and global w rite l i nes are all deactivated.
6-76
MOD E L 3562A
uest i s