Interrupt Acknowledge Cycle Flowchart - Motorola MC68020 User Manual

The interrupt acknowledge cycle is a read cycle. It differs from the read cycle described in
5.3.1 Read Cycle in that it accesses the CPU address space. Specifically, the differences
are:
1. FC2–FC0 are set 111 for CPU address space.
2. A3, A2, and A1 are set to the interrupt request level (the inverted values of IPL2,
IPL1, and IPL0, respectively).
3. The CPU space type field (A19–A16) is set to 1111, the interrupt acknowledge code.
4. Other address signals (A31–A20, A15–A4, and A0 for the MC68020; A23–A20,
A15–A4, and A0 for the MC68EC020) are set to one.
The responding device places the vector number on the data bus during the interrupt
acknowledge cycle. Beyond this, the cycle is terminated normally with DSACK1/DSACK0.
Figure 5-32 is the flowchart of the interrupt acknowledge cycle.
Figure 5-33 shows the timing for an interrupt acknowledge cycle terminated with
DSACK1/DSACK0.
PROCESSOR
ACKNOWLEDGE INTERRUPT
1) INTERRUPT PENDING CONDITION (IPEND FOR
MC68020) RECOGNIZED BY CURRENT INSTRUC-
TION—WAIT FOR INSTRUCTION BOUNDARY.
2) SET R/W TO READ
3) SET FUNCTION CODE TO CPU SPACE
4) PLACE INTERRUPT LEVEL ON A1, A2, AND A3.
TYPE FIELD = IACK
5) SET SIZE TO BYTE
* 6) NEGATE IPEND
7) ASSERT AS AND DS
ACQUIRE VECTOR NUMBER
1) LATCH VECTOR NUMBER
2) NEGATE AS AND DS
CONTINUE INTERRUPT EXCEPTION PROCESSING
*
This step does not apply to the MC68EC020.
Figure 5-32. Interrupt Acknowledge Cycle Flowchart
5-46
1) PLACE VECTOR NUMBER ON LEAST
2) ASSERT DSACK1/DSACK0
1) REMOVE VECTOR NUMBER FROM DATA BUS
2) NEGATE DSACK1/DSACK0
M68020 USER'S MANUAL
INTERRUPTING DEVICE
REQUEST INTERRUPT
PROVIDE VECTOR INFORMATION
SIGNIFICANT BYTE OF DATA PORT
(DEPENDS ON PORT SIZE)
OR
ASSERT AVEC FOR AUTOMATIC GENERA-
TION OF VECTOR NUMBER
RELEASE
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