Data Bus Activity For Byte, Word, And Long-Word Ports - Motorola MC68020 User Manual

Table 9-1. Data Bus Activity for Byte, Word, and Long-Word Ports
Transfer Size SIZ1
Byte
Word
3 Bytes
Long Word
During cachable read cycles, the addressed device must provide valid data over its full
bus width as indicated by DSACK1 / DSACK0 . While instructions are always prefetched as
long-word-aligned accesses, data fetches can occur with any alignment and size.
Because the MC68020/EC020 assumes that the entire data bus port size contains valid
data, cachable data read bus cycles must provide as much data as signaled by the port
size during a bus cycle. To satisfy this requirement, the R/ W signal must be included in
the byte select logic for the MC68020/EC020.
Figure 9-5 shows a block diagram of an MC68020/EC020 system with a single memory
bank. The PAL provides memory-mapped byte select signals for an asynchronous 32-bit
port and unmapped byte select signals for other memory banks or ports. Figure 9-6
provides sample equations for the PAL.
The PAL equations and circuits presented here cannot be the optimal implementation for
every system. Depending on the CPU clock frequency, memory access times, and system
architecture, different circuits may be required.
9-6
SIZ0 A1
0 1 0
0 1 0
0 1 1
0 1 1
1 0 0
1 0 0
1 0 1
1
1 0
1 1 0
1 1 0
1 1 1
1 1 1
0 0 0
0 0 0
0 0 1
0 0 1
M68020 USER'S MANUAL
Data Bus Active Sections
Byte (B), Word (W), Long-Word (L) Ports
A0 D31–D24 D23–D16
0 B W L
1 B
0 B W
1 B
0 B W L
1 B
0 B W
1 B
0 B W L
1 B
B W
0
1 B
0 B W L
1 B
0 B W
1 B
D15–D8
— —
W L —
— L
W —
W L —
W L L
W L
W —
W L L
W L L
W L
W —
W L L
L
W L
W L
W —
D7–D0
—
—
—
L
—
—
L
L
—
L
L
L
L
L
L
L
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