Processor Activity For Example 4 - Motorola MC68020 User Manual

CLOCK
BUS
ACTIVITY
BUS
CONTROLLER
SEQUENCER
INSTRUCTION
EXECUTION TIME
CLOCK
COUNTER
Figure 8-6 shows the same instruction stream executing with four clocks for every read
and write. The idle bus cycles coincide with the wait states of the memory access;
therefore, the total execution time is only 13 clocks.
Examples 1–4 demonstrate the complexity of instruction timing calculation for the
MC68020/EC020. It is impossible to anticipate individual instruction timing as an absolute
number of clock cycles due to the dependency of overlap on the instruction sequence and
alignment as well as the number of wait states in memory. This can be seen by comparing
individual and composite time for Figures 8-3 through 8-6. These instruction timings are
compared in Table 8-1, where timing varies for each instruction as the context varies.
Table 8-1. Examples 1–4 Instruction Stream Execution Comparison
Instruction
#1) MOVE.L D4,(A1)+
#2) ADD.L D4,D5
#3) MOVE.L (A1),–(A2)
#4) ADD.L D5,D6
Total Clock Cycles
8-8
1 2 4 5
3
WRITE
WRITE TO (A1)+
IDLE
CALCULATE
PERFORM PERFORM
SOURCE EA
MOVE #1 ADD #2
MOVE.L D4,(A1)+
(5)
LEGEND:
1) MOVE.L D4,(A1)+
2) ADD.L D4,D5
3) MOVE.L (A1),–(A2)
4) ADD.L D5,D6
Figure 8-6. Processor Activity for Example 4
Example 1
(Odd Alignment)
6
0
9
1
16
M68020 USER'S MANUAL
6 8 9
7
READ
READ FROM (A1)
CALCULATE
DESTINATION
IDLE
EA
MOVE #3
MOVE #3
MOVE.L (A1),–(A2)
Example 2
(Even Alignment)
4
3
6
3
16
10 11 12 13 14
WRITE
WRITE TO –(A2)
PERFORM PERFORM
MOVE #3 ADD #4
(8)
Example 4
Example 3 (Cache with
(Cache) Wait States)
4
0
7
1
12
5
0
8
0
13
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