Processor Activity For Example 2 - Motorola MC68020 User Manual

Example 2
Using the same instruction stream, the second example demonstrates the different effects
of instruction execution overlap on instruction timing when the same instructions are
positioned slightly differently in 32-bit memory:
The assumptions for example 2 (see Figure 8-4) are:
1. The data bus is 32 bits,
2. The first instruction is prefetched from an even-word address,
3. Memory access occurs with no wait states, and
4. The cache is disabled.
1 2
CLOCK
BUS
ACTIVITY
BUS
IDLE
CONTROLLER
PERFORM
SEQUENCER
MOVE #1
INSTRUCTION
MOVE.L D4,(A1)+
EXECUTION TIME
CLOCK
COUNTER
LEGEND:
Although the total execution time of the instruction segment does not change in this
example, the individual instruction times are significantly different. This example
demonstrates that the effects of overlap are not only instruction-sequence dependent but
are also dependent upon the alignment of the instruction stream in memory.
8-6
Address n
n + 4
n + 8
4 5 6
3
WRITE PREFETCH
PREFETCH
WRITE TO (A1)+
BYTES n + 8
CALCULATE
PERFORM
SOURCE EA
ADD #2
MOVE #3
ADD.L D4,D5
(4) (3)
1) MOVE.L D4,(A1)+
2) ADD.L D4,D5
3) MOVE.L (A1),–(A2)
4) ADD.L D5,D6
Figure 8-4. Processor Activity for Example 2
M68020 USER'S MANUAL
MOVE #1
MOVE #3
•••
8 9 10 11
7
READ
READ FROM (A1)
CALCULATE
PERFORM
DESTINATION
IDLE
IDLE
EA
MOVE #3
MOVE.L (A1),–(A2)
(6)
ADD #2
ADD #4
•••
12 13 14 15
WRITE PREFETCH
PREFETCH
WRITE TO –(A2)
BYTES n + 12
PERFORM NEXT
MOVE #3 ADD #4 INSTRUCTION
ADD.L D5,D6
(3)
16 17
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