Chip Select Pal Equations - Motorola MC68020 User Manual

PAL16L8
FPCP CS GENERATION CIRCUITRY FOR 25 MHz OPERATION
MOTOROLA INC., AUSTIN, TEXAS
INPUTS: CLK ~AS
OUTPUTS: ~CS CLKD
!~CS = FC2
*!A19
*!A15
*!CLK
+FC2
*!A19
*!A15
*!~AS
+FC2
*!A19
*!A15
*CLKD
CLKD = CLK
Description: There are three terms to the CS generation. The first term denotes the earliest time CS can be asserted.
The second term is used to assert CS until the end of the FPCP access. The third term is to ensure that no race
condition occurs in case of a late AS .
CLK
AS
CS
DSACK1/DSACK0
START
9-4
FC2 FC1 FC0 A19
*FC1 *FC0
*!A18 *A17
*!A14 *A13
*FC1 *FC0
*!A18 *A17
*!A14 *A13
*FC1 *FC0
*!A18 *A17
*!A14 *A13
Figure 9-3. Chip Select PAL Equations
9
19
FPCP SPECIFICATION
Figure 9-4. Bus Cycle Timing Diagram
M68020 USER'S MANUAL
A18 A17 A16 A15
;cpu space = $7
*!A16 ;coprocessor access = $2
;coprocessor id = $1
;qualified by MPU clock low
;cpu space = $7
*!A16 ;coprocessor access = $2
;coprocessor id = $1
;qualified by address strobe low
;cpu space = $7
*!A16 ;coprocessor access = $2
;coprocessor id = $1
;qualified by CLKD (delayed CLK)
47A
A14 A13
8
MPU SPECIFICATION
MOTOROLA