Motorola MC68020 User Manual page 90

State 0
MC68020—The processor asserts ECS and OCS in S0 to indicate the beginning of an
external operand cycle. The processor also asserts RMC in S0 to identify a read-
modify-write cycle. The processor places a valid address on A31–A0 and valid function
codes on FC2–FC0. The function codes select the address space for the operation.
SIZ1, SIZ0 become valid in S0 to indicate the operand size. The processor drives R/W
high for the read cycle.
MC68EC020—The processor asserts RMC in S0 to identify a read-modify-write cycle.
The processor places a valid address on A23–A0 and valid function codes on FC2–
FC0. The function codes select the address space for the operation. SIZ1–SIZ0
become valid in S0 to indicate the operand size. The processor drives R/W high for the
read cycle.
State 1
MC68020—One-half clock later in S1, the processor asserts AS to indicate that the
address on the address bus is valid. The processor also asserts DS during S1. In
addition, the ECS (and OCS, if asserted) signal is negated during S1.
MC68EC020—One-half clock later in S1, the processor asserts AS to indicate that the
address on the address bus is valid. The processor also asserts DS during S1.
State 2
MC68020—During S2, the processor asserts DBEN to enable external data buffers. The
selected device uses R/W , SIZ1, SIZ0, A1, A0, and DS to place information on the
data bus. Any or all of the bytes (D31–D24, D23–D16, D15–D8, and D7–D0) are
selected by SIZ1, SIZ0, A1, and A0. Concurrently, the selected device may assert the
DSACK1/DSACK0 signals.
MC68EC020—During S2, the selected device uses R/W, SIZ1, SIZ0, A1, A0, and DS to
place information on the data bus. Any or all of the bytes (D31–D24, D23–D16, D15–
D8, and D7–D0) are selected by SIZ1, SIZ0, A1, and A0. Concurrently, the selected
device may assert the DSACK1/DSACK0 signals.
State 3
MC68020/EC020—As long as at least one of the DSACK1/DSACK0 signals is
recognized by the end of S2 (meeting the asynchronous input setup time requirement),
data is latched on the next falling edge of the clock, and the cycle terminates. If
DSACK1/DSACK0 is not recognized by the start of S3, the processor inserts wait
states instead of proceeding to S4 and S5. To ensure that wait states are inserted,
both DSACK0 and DSACK1 must remain negated throughout the asynchronous input
setup and hold times around the end of S2. If wait states are added, the processor
continues to sample the DSACK1/DSACK0 signals on the falling edges of the clock
until one is recognized.
State 4
MC68020/EC020—At the end of S4, the processor latches the incoming data.
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