Motorola MC68020 User Manual page 122

State changes occur on the next rising edge of the clock after the internal signal is
recognized as valid. The BG signal transitions on the falling edge of the clock after a state
is reached during which G changes. The bus control signals (controlled by T) are driven
by the processor immediately following a state change when bus mastership is returned to
the MC68EC020.
State 0, at the top center of the diagram, in which both G and T are negated, is the state
of the bus arbiter while the processor is bus master. Request R keeps the arbiter in state 0
as long as it is negated. When a request R is received, both grant G and signal T are
asserted (in state 1 at the top left). The next clock causes a change to state 2, at the lower
left, in which G and T are held. The bus arbiter remains in that state until request R is
negated. Then the arbiter changes to the center state, state 3, and negates grant G. The
next clock takes the arbiter to state 4, at the upper right, in which grant G remains negated
and signal T remains asserted. The arbiter returns to the original state, state 0, and
negates signal T. This sequence of states follows the normal sequence of signals for
relinquishing the bus to an external bus master. Other states apply to other possible
sequences of R.
The MC68EC020 does not allow arbitration of the external bus during the read-modify-
write sequence. For the duration of this sequence, the MC68EC020 ignores the BR input.
If mastership of the MC68EC020 bus is required during a read-modify-write operation,
BERR must be used to abort the read-modify-write sequence. The bus arbitration
sequence while the bus is inactive (i.e., executing internal operations such as a multiply
instruction) is shown in Figure 5-49.
5-74 M68020 USER'S MANUAL MOTOROLA