Fetch Effective Address - Motorola MC68020 User Manual

8.2.1 Fetch Effective Address

The fetch effective address table indicates the number of clock periods needed for the
processor to calculate and fetch the specified effective address. The total number of clock
cycles is outside the parentheses; the number of read, prefetch, and write cycles is given
inside the parentheses as (r/p/w). These cycles are included in the total clock cycle
number.
Address Mode
Dn
An
(An)
(An)+
–(An)
(d ,An) of (d ,PC)
16 16
(xxx).W
(xxx).L
#<data >.B
#<data >.W
#<data >.L
(d 8 ,An,Xn) or (d 8 ,PC,Xn)
(d ,An,Xn) or (d ,PC,Xn)
16 16
(B)
(d ,B)
16
(d ,B)
32
([B],I)
([B],I,d )
16
([B],I,d )
32
([d ,B],I)
16
([d ,B],I,d )
16 16
([d ,B],I,d )
16 32
([d ,B],I)
32
([d ,B],I,d )
32 16
([d ,B],I,d )
32 32
B = Base address; 0, An, PC, Xn, An + Xn. Form does not affect timing.
I = Index; 0, Xn
NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing.
MOTOROLA
Best Case
M68020 USER'S MANUAL
Cache Case
0(0/0/0) 0(0/0/0)
0(0/0/0) 0(0/0/0)
3(1/0/0) 4(1/0/0)
4(1/0/0) 4(1/0/0)
3(1/0/0) 5(1/0/0)
3(1/0/0) 5(1/0/0)
3(1/0/0) 4(1/0/0)
3(1/0/0) 4(1/0/0)
0(0/0/0) 2(0/0/0)
0(0/0/0) 2(0/0/0)
0(0/0/0) 4(0/0/0)
4(1/0/0) 7(1/0/0)
4(1/0/0) 7(1/0/0)
4(1/0/0) 7(1/0/0)
6(1/0/0) 9(1/0/0)
10(1/0/0) 13(1/0/0)
9(2/0/0) 12(2/0/0)
11(2/0/0) 14(2/0/0)
11(2/0/0) 14(2/0/0)
11(2/0/0) 14(2/0/0)
13(2/0/0) 16(2/0/0)
13(2/0/0) 16(2/0/0)
15(2/0/0) 18(2/0/0)
17(2/0/0) 20(2/0/0)
17(2/0/0) 20(2/0/0)
Worst Case
0(0/0/0)
0(0/0/0)
4(1/0/0)
4(1/0/0)
5(1/0/0)
6(1/1/0)
6(1/1/0)
7(1/1/0)
3(0/1/0)
3(0/1/0)
5(0/1/0)
8(1/1/0)
9(1/1/0)
9(1/1/0)
12(1/1/0)
16(1/2/0)
13(2/1/0)
16(2/1/0)
17(2/2/0)
16(2/1/0)
19(2/2/0)
20(2/2/0)
20(2/2/0)
22(2/2/0)
24(2/3/0)
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