Bus Arbitration Control (Mc68020) - Motorola MC68020 User Manual

5.7.1.4 BUS ARBITRATION CONTROL (MC68020). The bus arbitration control unit in the
MC68020 is implemented with a finite state machine. As discussed previously, all
asynchronous inputs to the MC68020 are internally synchronized in a maximum of two
cycles of the processor clock.
As shown in Figure 5-44, input signals labeled R and A are internally synchronized
versions of the BR and BGACK signals, respectively. The BG output is labeled G, and the
internal high-impedance control signal is labeled T. If T is true, the address, data, and
control buses are placed in the high-impedance state after the next rising edge following
the negation of AS and RMC. All signals are shown in positive logic (active high),
regardless of their true active voltage level.
Figure 5-44. MC68020 Bus Arbitration State Diagram
MOTOROLA
RA
GT
STATE 1
XX
RA
XA
GT
STATE 2
RA
RA
R—BUS REQUEST
A—BUS GRANT ACKNOWLEDGE
G—BUS GRANT
T—THREE-STATE CONTROL TO BUS CONTROL LOGIC
X—DON'T CARE
NOTE: The BG output will not be asserted while RMC is asserted.
M68020 USER'S MANUAL
RA
XA
GT
STATE 0
RA
XX
GT
STATE 3
RX
GT
XX
STATE 6
RA
RA
GT
STATE 4
RX
GT
STATE 5
5- 67