Using Software To Complete The Bus Cycles - Motorola MC68020 User Manual

stack for stage B of the pipe are accepted as valid; the processor assumes that there is
no prefetch pending for stage B and that software has repaired or filled the image of
stage B, if necessary.
1 = Rerun faulted bus cycle or run pending prefetch
0 = Do not rerun bus cycle
Bits 11–9—Reserved by Motorola
DF—Fault/Rerun Flag
If the DF bit is set, a data fault has occurred and caused the exception. If the DF bit is
set when the processor reads the stack frame, it reruns the faulted data access;
otherwise, it assumes that the data input buffer value on the stack is valid for a read or
that the data has been correctly written to memory for a write (or that no data fault
occurred).
1 = Rerun faulted bus cycle or run pending prefetch
0 = Do not rerun bus cycle
RM—Read-Modify-Write
1 = Read-modify-write operation on data cycle
0 = Not a read-modify-write operation
RW—Read/Write
1 = Read on data cycle
0 = Write on data cycle
SIZE—Size Code
The SIZE field indicates the size of the operand access for the data cycle.
Bit 3—Reserved by Motorola
FC2–FC0—Specifies the address space for data cycle

6.2.2 Using Software to Complete the Bus Cycles

One method of completing a faulted bus cycle is to use a software handler to emulate the
cycle. This is the only method for correcting address errors. The handler should emulate
the faulted bus cycle in a manner that is transparent to the instruction that caused the
fault. For instruction stream faults, the handler may need to run bus cycles for both the B
and C stages of the instruction pipe. The RB and RC bits of the SSW identify the stages
that may require a bus cycle; the FB and FC bits of the SSW indicate that a stage was
invalid when an attempt was made to use its contents. Those stages must be repaired.
For each faulted stage, the software handler should copy the instruction word from the
proper address space as indicated by the S-bit of the copy of the SR saved on the stack to
the image of the appropriate stage in the stack frame. In addition, the handler must clear
the RB or RC bit associated with the stage that it has corrected. The handler should not
change the FB and FC bits.
6-24 M68020 USER'S MANUAL MOTOROLA