Jump Effective Address - Motorola MC68020 User Manual

8.2.5 Jump Effective Address

The jump effective address table indicates the number of clock periods needed for the
processor to calculate the specified effective address. Fetch time is only included for the
first level of indirection on memory indirect addressing modes. The total number of clock
cycles is outside the parentheses; the number or read, prefetch, and write cycles is given
inside the parentheses as (r/p/w). These cycles are included in the total clock cycle
number.
Address Mode
(An)
(d ,An)
16
(xxx).W
(xxx).L
(d ,An,Xn) or (d ,PC,Xn)
8 8
(d ,An,Xn) or (d ,PC,Xn)
16 16
(B)
(B,d )
16
(B,d )
32
([B],I)
([B],I,d )
16
([B],I,d )
32
([d ,B],I)
16
([d ,B],I,d )
16 16
([d ,B],I,d )
16 32
([d ,B],I)
32
([d ,B],I,d )
32 16
([d ,B],I,d )
32 32
B = Base address; 0, An, PC, Xn, An + Xn, PC + Xn. Form does not affect timing.
I = Index; 0, Xn
NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing.
MOTOROLA
Best Case
10(1/0/0)
10(1/0/0)
10(1/0/0)
12(1/0/0)
12(1/0/0)
14(1/0/0)
16(1/0/0)
16(1/0/0)
M68020 USER'S MANUAL
Cache Case
0(0/0/0) 2(0/0/0)
1(0/0/0) 4(0/0/0)
0(0/0/0) 2(0/0/0)
0(0/0/0) 2(0/0/0)
3(0/0/0) 6(0/0/0)
3(0/0/0) 6(0/0/0)
3(0/0/0) 6(0/0/0)
5(0/0/0) 8(0/0/0)
9(0/0/0) 12(0/0/0)
8(1/0/0) 11(1/0/0)
13(1/0/0)
13(1/0/0)
13(1/0/0)
15(1/0/0)
15(1/0/0)
17(1/0/0)
19(1/0/0)
19(1/0/0)
Worst Case
2(0/0/0)
4(0/0/0)
2(0/0/0)
2(0/0/0)
6(0/0/0)
6(0/0/0)
6(0/0/0)
8(0/1/0)
12(0/1/0)
11(1/1/0)
14(1/1/0)
14(1/1/0)
14(1/1/0)
17(1/1/0)
17(1/1/0)
19(1/2/0)
21(1/2/0)
23(1/2/0)
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