9/29/95
LIST OF ILLUSTRATIONS (Concluded)
Figure
Number
7-45
MC68020/EC020 Postinstruction Stack Frame................................................ 7-48
8-1
Concurrent Instruction Execution ..................................................................... 8-3
8-2
Instruction Execution for Instruction Timing Purposes ..................................... 8-3
8-3
8-4
8-5
8-6
9-1
9-2
9-3
9-4
Bus Cycle Timing Diagram ............................................................................... 9-4
9-5
9-6
9-7
High-Resolution Clock Controller ..................................................................... 9-11
9-8
Alternate Clock Solution ................................................................................... 9-11
9-9
9-10
Module Descriptor Format ................................................................................ 9-15
9-11
Module Entry Word .......................................................................................... 9-15
9-12
Module Call Stack Frame ................................................................................. 9-16
9-13
10-1
10-2
10-3
10-4
10-5
A-1
Bus Arbitration Circuit-MC68EC020 (Two-Wire) to DMA (Three-Wire) ......... A-1
MOTOROLA
SECTION 1: OVERVIEW
Title
M68020 USER'S MANUAL
UM Rev 1
Page
Number
xvii