Mc68020/Ec020 On-Chip Cache Organization - Motorola MC68020 User Manual

F F F
C C C
2 1 0
Figure 4-1. MC68020/EC020 On-Chip Cache Organization
When an instruction fetch occurs, the cache (if enabled) is first checked to determine if the
word required is in the cache. This check is achieved by first using the index field (A7–A2)
of the access address as an index into the on-chip cache. This index selects one of the 64
entries in the cache. Next, A31–A8 and FC2 are compared to the tag of the selected entry.
(Note that in the MC68EC020, A31–A24 are used for internal on-chip cache tag
comparison.) If there is a match and the valid bit is set, a cache hit occurs. A1 is then used
to select the proper word from the cache entry, and the cycle ends. If there is no match or
if the valid bit is clear, a cache miss occurs, and the instruction is fetched from external
memory. This new instruction is automatically written into the cache entry, and the valid bit
is set unless the F-bit in the CACR is set. Since the processor always prefetches
instructions externally with long-word-aligned bus cycles, both words of the entry will be
updated, regardless of which word caused the miss.
Data accesses are not cached, regardless of their associated
address space.
4–2
MC68020/EC020 PREFETCH ADDRESS
A A A A A A
3 2 2 2 2 1
1 3 2 1 0 9
TAG
1 OF
64 SELECT
TAG REPLACE
COMPARATOR
M68020 USER'S MANUAL
A A A A A A A A A
1 1 1 1 1 1 1 1 1
8 7 6 5 4 3 2 1 0
TAG
WORD SELECT
V WORD
VALID
ENTRY HIT
LINE
HIT
NOTE
A A A A A A A A
9 8 7 6 5 4 3 2
INDEX
WORD
REPLACEMENT
DATA
TO
INSTRUCTION
PATH
CACHE
CONTROL
A A
1 0
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