Processor Dependent Hardware Controller; Dual Serial Controller; Field Programmable Gate Array - HP Integrity rx2620 User's & Service Manual

Processor Dependent Hardware Controller

The PDH controller provides these features:
16-bit PDH bus with reserved address space for the following:
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Flash memory
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Nonvolatile memory
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Scratch RAM
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Real-time Clock
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UARTs
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External registers
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Firmware read/writable registers
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Two general purpose 32-bit registers
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Semaphore registers
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Monarch selection registers
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Test and Reset register
Reset and INIT generation

Dual Serial Controller

The dual serial controller is a dual universal asynchronous receiver and transmitter
(DUART). This chip provides enhanced UART functions with 16-byte first-in, first-out
(FIFO), a modem control interface. Registers on this chip provide onboard error
indications and operation status. An internal loopback capability provides onboard
diagnostics.
Features include:
Data rates up to 115.2 kbps
16550A fully compatible controller
A 16-byte transmit FIFO that reduces the bandwidth requirement of the external
CPU
A 16-byte receive FIFO with four selectable interrupt trigger levels and error flags
that reduce the bandwidth requirement of the external CPU
UART control that provides independent transmit and receive
Modem control signals (-CTS, -RTS, -DSR, -DTR, -RI, -CD, and software
controllable line break)
Programmable character lengths (5, 6, 7, 8) with Even, Odd or No Parity
A status report register

Field Programmable Gate Array

The field programmable gate array (FPGA) provides ACPI and LPC support for the
PDH bus and provides these features:
ACPI 2.0 interface
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