Remote I/O Link; Memory Interface-Memory Multiplexer; Processor Dependent Hardware - HP Integrity Superdome SX1000 User Manual

Overview
Cell Board
either 18 or 19 bits. The other four bundles are used for output data and are also either 18 or 19 bits in width.
The crossbar link has a built-in link presence detect capability that effectively prevents either the CC or the
crossbar from driving signals into an unpowered device on the opposite side of the link.

Remote I/O Link

The remote I/O link is a self-correcting, high-speed interface that connects between the CC and the SBA
through a pair of differential cables. This differential link has one input differential data "bundle" and one
output differential data "bundle," each with a differential strobe for synchronization. The link achieves a peak
data transfer rate of 1 GB/s. Embedded inside each of the cables is a differential signal pair that sends utility
subsystem information through the cables from a core I/O card plugged in to the remote I/O Backplane. This
utility information allows for the diagnosis of various cable interconnect problems that might be encountered
during system installation, maintenance, or normal operation. The differential link has a built-in presence
detect capability that effectively prevents either the CC or SBA/LBA from driving signals into an unpowered
device on the opposite side of the link.
Memory Interface—Memory Multiplexer
The memory interface of the Memory Multiplexer (MM—shown in Figure 1-6 as JAB) multiplexes and
demultiplexes data between the CC and the SDRAM in the memory subsystem. The data portion of the
memory subsystem enters and exits the CC on four 72-bit wide Memory Interface Data (MID) buses, each bus
running at 500 MT/s. The MID bus provides an independent access path to memory, with its own address bus,
control bus, data bus, the MMs, and DIMMs. Only the data and TAG portions of the memory subsystem are
routed through the MM devices. All address and control signals to the DIMMs are generated by the CC and
are sent directly to the DIMMs by way of memory interface address and control buses. This results in lower
memory latency.

Processor Dependent Hardware

The PDH uses an Intel 80C251 embedded micro controller and a USB interface chip to provide hardware
resources required for both system and utility firmware. The utility subsystem employs an intelligent
interface that is capable of passing multiple forms of information between system firmware and the MP by
way of the PDHC.
Features provided by the PDH hardware include:
• 512 KB Flash EPROM for PDHC boot-strap code storage
• 512 KB PDHC SRAM for operational instruction and data storage
• Disposal CPLD provides memory-mapped Cars to control the cell board for multiple utility subsystem
needs
• System Management Bus (Snubs) for reading of the processor EEPROM, scratch EEPROM, and thermal
sensing device
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• I C Bus for reading PDH, cell board, and cell power board FRU identification information
• Control and monitoring of cell board local power
• Timing control of cell board reset signals
• Logic analyzer port for accessing PDH signals
• Arbitration between the processors (system firmware) and the utility subsystem to allow the utility
subsystem access to PDH peripheral components, which include:
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Chapter 1