Processor Sockets; Processor Bus; Zx1 I/O And Memory Controller; Memory - HP Integrity rx2620 User's & Service Manual

"Processor Bus" (page 15)
"ZX1 I/O and Memory Controller" (page 15)
"Memory" (page 15)
"I/O Bus Interface" (page 17)
"Processor Dependent Hardware Controller" (page 18)
"Dual Serial Controller" (page 18)
"Field Programmable Gate Array" (page 18)
"Baseboard Management Controller" (page 19)
"SCSI Controller" (page 19)
"IDE Interface" (page 19)
"1 Gb System LANs A and B" (page 19)
"USB Connectors" (page 20)
"Data Pathing Information" (page 20)

Processor Sockets

The system board consists of two zero insertion force (ZIF) processor sockets, the
core electronic complex (CEC), and circuitry for clock and power generation and
distribution, boundary scan, in-target probe, and debug.
The front side bus (FSB) is the IA64 processor bus, based on bus protocol from Intel.
Unlike previous PA-RISC microprocessors that utilized Hewlett Packard Enterprise
proprietary processor buses, this processor is designed to utilize the FSB. This allows
processor field replaceable units (FRUs) to be dropped in, provided that electrical
and mechanical compatibility and support circuitry exist. For the purposes of this
document, a FRU consists of a single processor with power pod, and the heat sink
assembly.
Each processor plugs directly into, and is powered by its own 12 V to 1.2 V power
pod. Other power for the system board comes from multiple on-board DC to DC
converters. Each processor is attached to the board through a ZIF socket and the
entire FRU secured by a heat sink.

Processor Bus

The FSB in this product runs at 200 MHz. Data on the FSB are transferred at a double
data rate, which allows a peak FSB bandwidth of 6.4 Gb/s.

ZX1 I/O and Memory Controller

The server supports the following features of the ZX1 I/O and memory controller chip:
8.5 Gb/s peak I/O bandwidth
Seven communication paths
Peak memory bandwidth of 8.5 Gb/s
Two memory cells, 144 data bits each

Memory

The memory subsystem provides two memory cells. Each cell is 144 data bits wide.
Each cell has six DIMM slots, which means a total of 12 DIMM slots are available.
The memory bus clock speed is 133 MHz, and the data transfer rate is 266
15