Processor Sockets; Processor Bus; Zx1 I/O And Memory Controller; Memory - HP Integrity rx2620 User's & Service Manual

• "Dual Serial Controller" on page 26
• "Field Programmable Gate Array" on page 26
• "Baseboard Management Controller" on page 27
• "SCSI Controller" on page 27
• "IDE Interface" on page 27
• "1 Gb System LANs A and B" on page 28
• "USB Connectors" on page 28
• "Data Pathing Information" on page 28

Processor Sockets

The system board consists of two zero insertion force (ZIF) processor sockets, the core electronic complex
(CEC), and circuitry for clock and power generation and distribution, boundary scan, in-target probe, and
debug.
The front side bus (FSB) is the IA64 processor bus, based on bus protocol from Intel. Unlike previous PA-RISC
microprocessors that utilized HP's proprietary processor bus, this processor is designed to utilize the FSB.
This allows processor field replaceable units (FRUs) to be dropped in, provided that electrical and mechanical
compatibility and support circuitry exist. For the purposes of this document, a FRU consists of a single
processor with power pod, and the heatsink assembly.
Each processor plugs directly into, and is powered by its own 12 V to 1.2 V power pod. Other power for the
system board comes from multiple on-board DC to DC converters. Each processor is attached to the board
through a ZIF socket and the entire FRU secured by a heatsink.

Processor Bus

The FSB in this product runs at 200 MHz. Data on the FSB are transferred at a double data rate, which
allows a peak FSB bandwidth of 6.4 Gb/sec.

ZX1 I/O and Memory Controller

The HP Integrity rx2620 server supports the following features of the ZX1 I/O and memory controller chip
• 8.5 Gb/s peak I/O bandwidth
• Seven communication paths
• Peak memory bandwidth of 8.5 Gb/s
• Two memory cells, 144 data bits each

Memory

The memory subsystem provides two memory cells, each of which is 144 data bits wide. Each cell has six
DIMM slots, which means a total of 12 DIMM slots are available. The memory bus clock speed is 133 MHz,
and the data transfer rate is 266 Mtransfers/second as data is clocked on both edges of the clock. The peak
data bandwidth for this memory subsystem design is 8.5 Gb/s. Load DIMMs in quads with qualified modules.
Memory is protected by data ECC, and the hardware implementation supports chip-spare.
The minimum amount of memory supported by the server is 1 GB (four 256 MB modules). The maximum
amount of memory supported by the server is 32 GB (eight 4 GB modules).
Chapter 1
Introduction
System Board Components
23