Pci Bus Latency; Table 3-2. Power Requirements - Motorola MVME2300 Series Installation And Use Manual

The MPC 603 is a 64-bit processor with 16KB on-chip caches (16KB data
cache and 16KB instruction cache). The MPC604R is a 64-bit processor
with 32KB on-chip caches (32KB data cache and 32KB instruction cache).
The Raven bridge controller ASIC provides the bridge between the
PowerPC microprocessor bus and the PCI local bus. Electrically, the
Raven chip is a 64-bit PCI connection. Four programmable map decoders
in each direction provide flexible addressing between the PowerPC
microprocessor bus and the PCI local bus.
The power requirements for the MVME2300 are shown in Table 3-2.
Configuration
200 MHz 603
333 MHz 604R

PCI Bus Latency

Writes to PCI can be posted. The read access latency for PCI-bound cycles
initiated by the MPC60x bus master consists of the following components:
T
start
T
arb
T
ac
T
delay
3-5

Table 3-2. Power Requirements

+5V Power
4.0A typical
4.75A maximum
4.7A typical
5.8A maximum
Start-up time (TS# to PCI bus Request). T
system clocks.
PCI bus arbitration time
PCI access time (FRAME# to TRDY#)
Delay time from TRDY# on PCI to TA# on 60X bus.
is 4 system clocks.
T
delay
Block Diagram
+12V and -12V Power
PMC-dependent
(Refer to Appendix A,
Specifications)
is 6
start
3