Pentek 6230 Operating Manual page 87

a
FEATURES
65 MSPS Guaranteed Sample Rate
40 MSPS Version Available
Sampling Jitter < 300 fs
100 dB Multitone SFDR
1.3 W Power Dissipation
Differential Analog Inputs
Digital Outputs
Two's Complement Format
3.3 V CMOS-Compatible
Data Ready for Output Latching
APPLICATIONS
Multichannel, Multimode Receivers
AMPS, IS-136, CDMA, GSM, Third Generation
Single Channel Digital Receivers
Antenna Array Processing
Communications Instrumentation
Radar, Infrared Imaging
Instrumentation
PRODUCT DESCRIPTION
The AD6644 is a high-speed, high-performance, monolithic
14-bit analog-to-digital converter. All necessary functions,
including track-and-hold (T/H) and reference, are included on-
chip to provide a complete conversion solution. The AD6644
provides CMOS-compatible digital outputs. It is the third genera-
tion in a wideband ADC family, preceded by the AD9042 (12-bit
41 MSPS) and the AD6640 (12-bit 65 MSPS, IF sampling.)
AV
AIN
A1
AIN
V
2.4V
REF
ENCODE
INTERNAL
TIMING
ENCODE
SoftCell is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
DV
CC CC
TH1 TH2
ADC1 DAC1
5
MSB
GND DMID OVR DRY D13
14-Bit, 40 MSPS/65 MSPS
Designed for multichannel, multimode receivers, the AD6644 is
part of ADI's new SoftCell™ transceiver chipset. The AD6644
achieves 100 dB multitone, spurious-free dynamic range (SFDR)
through the Nyquist band. This breakthrough performance eases
the burden placed on multimode digital receivers (software radios)
which are typically limited by the ADC. Noise performance is
exceptional; typical signal-to-noise ratio is 74 dB.
The AD6644 is also useful in single channel digital receivers
designed for use in wide-channel bandwidth systems (CDMA,
W-CDMA). With oversampling, harmonics can be placed out-
side the analysis bandwidth. Oversampling also facilitates the use of
decimation receivers (such as the AD6620), allowing the noise
floor in the analysis bandwidth to be reduced. By replacing tradi-
tional analog filters with predictable digital components, modern
receivers can be built using fewer "RF" components, resulting
in decreased manufacturing costs, higher manufacturing yields,
and improved reliability.
The AD6644 is built on Analog Devices' high-speed complemen-
tary bipolar process (XFCB) and uses an innovative, multipass
circuit architecture. Units are packaged in a 52-terminal Low-
Profile Quad Plastic Flatpack (LQFP) specified from –25°C
to +85°C.
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate is 65 MSPS.
2. Fully differential analog input stage.
3. Digital outputs may be run on 3.3 V supply for easy interface
to digital ASICs.
4. Complete Solution: reference and track-and-hold.
5. Packaged in small, surface-mount, plastic, 52-terminal LQFP.
A2 TH3
ADC2
DIGITAL ERROR CORRECTION LOGIC
D12 D11 D10 D9 D8 D7
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
A/D Converter
TH4 TH5
ADC3
DAC2
AD6644
5
D6 D5 D4 D3 D2 D1
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
AD6644
6
LSB
D0