Pentek 6230 Operating Manual page 161

GC4016 MULTI-STANDARD QUAD DDC CHIP
ADDRESS 19: Output Frame Control, Suggested default = (see Table 3)
BIT TYPE
0-5 (LSB) R/W
6-7 (MSB) R/W
© GRAYCHIP,INC.
This document contains information which may be changed at any time without notice
NAME DESCRIPTION
FRAME_LENGTH Used in the serial and nibble modes to set the frame length, and is not used in
the microprocessor, link or parallel modes.
Serial, nibble modes:
Microprocessor, link or parallel modes:
SFS_MODE Used in the serial, nibble and parallel modes to set the frame strobe modes. Not
used in the microprocessor or link modes.
Serial mode: (See Figure 15)
Link mode:
Parallel mode: (See Figure 16)
Microprocessor or link modes:
The output frame length is (FRAME_LENGTH+1) in words (not complex
pairs). The frame length must be equal or greater than the number of
output words on the serial port. Values larger than the number of output
words can be useful to smooth the data output rate by slowing down the
output frame rate. The output frame rate must be at least as fast as the
average output data rate.
In the 16 bit nibble mode (BITS_PER_WORD=0), FRAME_LENGTH must
be greater than or equal to one (a frame length of at least two words).
If this is the master chip in a multi-chip TDM mode (FRAME_LENGTH+1)
sets the TDM frame length. The master chip will occupy the first
(WORDS_PER_FRAME+1) time slots of the frame.
If this is a slave chip, then (FRAME_LENGTH+1) is the delay, in number of
words, from the start of frame before outputting its data.
Unused, set to 0
In the serial mode SFS is active for one SCK cycle ahead of the first bit.
If SFS_MODE=0 (or = 2), then SFS is active for one SCK cycle at the start
of the frame.
If SFS_MODE=1, then SFS is active once for each I word.
If SFC=3 then SFS is active for each word (I or Q).
The SFS behavior in the nibble mode is similar except the frame strobe
occurs concurrent with the first nibble rather than 1 SCK cycle early.
In the parallel mode, SFS and RDY are used as flags to indicate valid
output data.
If SFS_MODE=0 or 1, then SFS is active for one SCK cycle when the I
sample is valid and RDY is active for one SCK cycle when Q is valid.
If SFS_MODE=2 or 3, then SFS is active for one SCK cycle when either I
or Q are valid and RDY is a start of frame signal which is active for when
the first I sample of an output block is valid (see BLOCK_SIZE address 20
and Figure 16). Note that when SFS_MODE=2 or 3 the RDY flag goes high
after the last word in a frame and goes low after the first word in the next
frame.
Unused, set to 0
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DATA SHEET REV 1.0
August 27, 2001