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6210
Pentek 6210 Manuals
Manuals and User Guides for Pentek 6210. We have
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Pentek 6210 manual available for free PDF download: Operating Manual
Pentek 6210 Operating Manual (170 pages)
Pentek Dual A/D Converter and Digital Receiver VIM Module for Pentek VIM Motherboards
Brand:
Pentek
| Category:
Media Converter
| Size: 2.41 MB
Table of Contents
Table of Contents
3
Copyright Information
2
Chapter 1: Overview
7
General Description
7
Input Section
7
A/D Converters
8
Connection to VIM Motherboard
8
Digital Drop Receivers
8
Simplified Block Diagram
9
Specifications
10
Chapter 2: Installation and Connections
13
Inspection
13
Jumper Blocks
13
External Clock Function Select Jumper
13
Model 6210 Front Panel Features
15
Duty Cycle Sensitivity
15
External Clock Input − EXT CLK
15
Analog Inputs − CH1 IN, CH2 in
17
Indicator Leds
17
Motherboard Leds − 0, 1, 2 & 3
18
Sync Bus Master LED − MAS
18
Sync Bus Terminator LED − TRM
18
Sync Bus − Serial I/O Connector
19
Signals for Synchronizing Multiple Boards
19
Mclk, Mclk
21
Prclk, Prclk
21
Msync, Msync
22
Sync1, Sync1
22
Compatibility with Other Products' Sync Buses
23
Sync2, Sync2
23
Sync Bus − Serial I/O Connector (Continued)
23
P0−Clkr1, P1−Clkr1
24
P0−Clks1, P1−Clks1
24
P0−Dr1, P1−Dr1
24
P0−Fsr1, P1−Fsr1
24
Serial Port Signals
24
P0−Clkx1, P1−Clkx1
25
P0−Dx1, P1−Dx1
25
P0−Fsx1, P1−Fsx1
25
Ttl−Sync
25
Installing the Model 6210 on a VIM Motherboard
26
Preparing the VIM Module for Installation
26
Figure 2−7: VIM Module Nylon Spacer
27
Installing the VIM Module on the VIM Motherboard
28
Figure 2−8: Model 4290 VIM Motherboard − Connectors & Mounting Holes
29
Chapter 3: Memory Map and Register Descriptions
31
Model 6210 Memory Map
31
Overview
31
Control Register
32
PROCCLK Frequency Divider
32
BIFO Disable
33
External Clock Enable
33
Termination Enable
33
Master / Slave
34
ID EEPROM Readout Register
32
Master Clock Divider
34
BIFO Decimation Register
35
Programmable Gain Amplifier
36
Loading the 12−Bit Gain Control Word
36
Data Format / Signal Path Register
38
Decimate DDR Input by 2
38
Pack Mode
38
Programmable−Gain Amplifier & Low−Pass Filter Bypass
40
DDR Bypass
41
SYNC Generate Register
41
Serial Port 0 Connection Register
42
The Other Processor's DDR
42
The Other Processor's Serial Port 0 Transmit Section
42
The Processor's Own DDR
42
Not Connected
43
CIC Gain Adjust Register
43
Processor Interface the HSP50214 DDR
43
Block Diagram
49
Ordering Information
49
Table of Contents
50
Pinout
52
Pin Descriptions
53
Functional Description
56
PDC Applications Overview
56
FDM Based Standards and Applications
56
TDM Based Standards and Applications
56
CDMA Based Standards and Applications
57
Traditional Modulation Formats
57
Resampling and Interpolation Filters
57
14-Bit Input and Processing Resolution
58
Summary
58
Input Section
58
Interpolation Example
59
Multiple Chip Synchronization
58
Input Level Detector
59
Figure 9
61
Carrier Synthesizer/Mixer
62
CIC Decimation Filter
64
CIC Gain Calculations
64
Using the Input Gain Adjust Control Signals
65
Halfband Decimating Filters
65
Examples of PROCCLK Rate Calculations
67
255-Tap Programmable FIR Filter
67
Programmable Downconverter
68
Automatic Gain Control (AGC)
68
Re-Sampler/Halfband Filter
73
Timing NCO
76
Cartesian to Polar Converter
78
Frequency Discriminator
79
Output Section
80
Parallel Direct Output Port Mode
80
Data Transitions
80
Data Ready Signal Assertion Rate
81
Serial Direct Output Port Mode
82
Serial Output Configuration Example 1
84
Serial Output Configuration Example 2
84
Buffer RAM Output Port
85
FIFO Operation Via 16-Bit Μprocessor Interface
86
FIFO Operation Via 8-Bit Μprocessor Interface
88
Snap Shot Operation
89
Avoiding Timing Pitfalls When Using the Buffer RAM Output Port
90
Microprocessor Write Section
90
Microprocessor Read Section
91
Applications
92
Composite Filter Response Example
92
RF/IF Considerations
92
PDC Configuration
93
References
93
Configuration Control Word Definitions
95
AC Test Load Circuit
107
Waveforms
108
Electrical Characteristics
154
E.1 Introduction
165
Table E−2: EEPROM Example (Model 6210 Shown)
166
F.1 Introduction
167
F.3 Calculating the Low Pass Bandwidth
168
F.6 Additional Information/References
169
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