Pentek 6230 Operating Manual page 143

GC4016 MULTI-STANDARD QUAD DDC CHIP
SIGNAL DESCRIPTION
A,B,C, DIN INPUT DATA, Active high input pins
The 14 bit 2's complement input data for the four channels. The inputs are clocked into the chip on the rising edge of the clock
(CK). These pins can be configured to support three 16 bit ports, two 14 bit differential ports, three 12 bit + 3 bit exponent ports, or
three 12 bit + 3 bit exponent + A/B selection ports. See Section 3.2 and Figure 18.
P[0:3] BIT SERIAL AND NIBBLE OUTPUT DATA, Active high tristate output pins
The nibble and bit serial output pins. In the serial mode these are individual outputs, in the nibble mode these form a four bit nibble
(P0 is normally the LSB of the Nibble, P3 is the MSB). The output bits are clocked out coincident with the rising edge of SCK (falling
edge if INV_SCK=1). These pins are tristated at power up and are enabled by EN_P0, EN_P1, EN_P2 and EN_P3.
P[0:23] PARALLEL OUTPUT DATA, Active high tri state output pins
The 24 bit parallel output port. These output bits are clocked out by CK coincident with the rising edge of SCK (falling edge if
INV_SCK=1) with the SFS and RDY pins used to identify valid data (Section 3.8.6). These pins are tristated at power up and are
enabled by the EN_PAR control register bit. These pins can are used in the wide word microprocessor mode. In this mode the pins
are used as part of the control bus when read from the data output page (See Section 3.8).
SCK SERIAL DATA CLOCK, Active high or low tristate output pin
The serial, nibble, link and parallel data output clock. The SCK signal is clocked out on the rising edge of CK. The SFS, RDY and
P output signals are clocked out of the chip coincident with the active edge of this clock. The active edge of the clock is user
programmable. This pin is tristated at power up and is enabled by the EN_SCK control register bit.
SFS SERIAL FRAME STROBE, Active high or low tristate output pin
The bit serial word strobe. This strobe identifies the beginning of a frame, a complex pair, or a word within bit serial output streams
as controlled by the SFS_MODE control register bits. The polarity of this signal is user programmable. This pin is tristated at power
up and is enabled by the EN_SFS control register bit. This pin is also used as a data valid signal for parallel outputs.
RDY READY FLAG, programmable active high or low bidirectional I/O pin
Used to identify when new outputs are available in the serial, nibble and microprocessor output modes. In the link mode RDY is an
input signal tied to the LACK output signal from SHARC DSP chips. In the parallel mode it is a data valid flag. The RDY signal is
clocked out on the rising edge of CK. This pin is tristated at power up and is enabled by the EN_RDY control register bit.
CK INPUT CLOCK. Active high input pin
The clock input to the chip. The AIN, BIN, CIN, DIN, DVAL, SIA and SIB input signals are clocked into the chip on the rising edge
of this clock. The SO, P, SFS, SCK and RDY outputs are clocked out on the rising edge of this clock.
DVAL DATA VALID. Active low input pin
This pin is normally grounded. This pin must be low to enable the internal clock. DVAL is clocked into the chip on the rising edge
of CK, and, if high, disables the following CK edge to the channels and resampler. It does not effect the clock to the output circuitry.
Since DVAL enables or disables the internal clock, it can be used as a data enable for non-continuous input data. This pin should
never be held high for more than 1ms. DVAL is used as a 2X clock input when the CK_2X_EN control bit is high (see Section 3.9).
SIA, SIB SYNC IN A and B. Active low input pins
The sync inputs to the chip. All timers, accumulators, and control counters (except the resampler time delay accumulator) are, or
can be, synchronized to SIA or SIB. These syncs are clocked into the chip on the rising edge of the input clock (CK).
SO SYNC OUT. Active low output pin
This signal is either a delayed version of one of the input syncs SIA or SIB, the sync counter's terminal count (TC), or a one-shot
strobe. The SO signal is clocked out of the chip on the rising edge of the input clock (CK).
C[0:7] CONTROL DATA I/O BUS. Active high bidirectional I/O pins
This is the 8 bit control data I/O bus. Control registers are written to or read from through these pins. The chip drives these pins
when CE is low, RD is low and WR is high. Note that when the output is in the wide word microprocessor mode, the P[0:23] pins
are used when reading and will behave the same as the C[0:7] pins. When reading from the output page the P[0:23] pins will output
data, when reading from all other pages the P[0:23] pins will read back high.
A[0:4] CONTROL ADDRESS BUS. Active high input pins
These pins are used to address the control registers within the chip. Each of the control registers within the chip are assigned a
unique address. A control register can be written to or read from by setting A[0:4] to the register's address and setting the page
register appropriately. An alternate method using a 4 bit addressing scheme is available to support using buses with limited
addressing (for example the TI320C6X family peripheral host interface bus). See Section 3.1.
RD READ ENABLE. Active low input pin
The register selected by A[0:4] and the page register is output on the C[0:7] pins when RD and CE are low.
WR WRITE ENABLE. Active low input pin
The value on the C[0:7] pins is written into the register selected by the A[0:4] and page register when WR and CE are low.
CE CHIP ENABLE. Active low input pin
This control strobe enables the read or write operations.
TCK,TDI,TMS,TDO
JTAG INTERFACE. Active high input (TCK, TMS, TDI) and tristate output (TDO) pins
The JTAG interface (See Section 3.15)
© GRAYCHIP,INC.
This document contains information which may be changed at any time without notice
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DATA SHEET REV 1.0
August 27, 2001