Pentek 6230 Operating Manual page 153

GC4016 MULTI-STANDARD QUAD DDC CHIP
ADDRESS 25: CFIR, Suggested default = 0x00
BIT TYPE
0 LSB R/W
1 R/W
2 R/W
3 R/W
4-6 R/W
7 R/W
ADDRESS 26: PFIR, Suggested default = 0x00
BIT TYPE
0 LSB R/W
1 R/W
2 R/W
3-4 R/W
5-7 R/W
ADDRESS 27: Input, Suggested default = 0x00
BIT TYPE
0-2 (LSBs) R/W
3 R/W
4-5 R/W
6 R/W
7 MSB R/W
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This document contains information which may be changed at any time without notice
NAME DESCRIPTION
NO_SYM_CFIR When this bit is high, CFIR is an 11 tap asymmetric filter. Coefficient h
multiplied by the newest data.
QDLY_CFIR Delay the Q sample stream by one CFIR input sample. Effectively, this is a 1/4
sample delay of the output PFIR. Used in the multi-channel modes (see Section
3.4).
IDLY_CFIR Delay the I-sample stream by one CFIR input sample. Effectively, this is a 1/4
sample delay of the output PFIR.Used in the multi-channel modes (see Section
3.4).
Unused
COARSE This introduces a gain of 2
feed CFIR. This allows optimization of gain in applications where it is known that
most of the signal energy presented to the A/D has been filtered out by the CIC. An
example of such an application is an FDM stack.
TEST Test mode. Should be set to 0.
NAME DESCRIPTION
NO_SYM_PFIR When this bit is high PFIR is an 32 tap asymmetric filter. Coefficient h
by the newest data.
QDLY_PFIR Delay the Q sample stream by one PFIR input sample. Effectively, this is a 1/2
sample delay of the output PFIR. Used in the real or multi-channel modes (see
Sections 3.3 and 3.4).
IDLY_PFIR Delay the I-sample stream by one PFIR input sample. Effectively, this is a 1/2
sample delay of the output PFIR.Used in the real or multi-channel modes (see
Sections 3.3 and 3.4).
PEAK_SELECT Select the overflow detection source for the peak counter. Only used if
PEAK_MODE=1. Selects CFIR, COARSE_GAIN, or PFIR for values 0,1, or 2
respectively (the values 2 and 3 are the same). See address 28 below.
Unused
NAME DESCRIPTION
INPUT_SEL Selects which input port to use for this channel. Values 0-3 select inputs A-D
respectively. Values 4 and 5 select differential inputs A and B. Values 6 and 7 select
the internal diagnostic source (see general address 5). Note that for differential
inputs one must also enable the differential receivers by setting the DIFF_IN bit in
register 4.
SEL_AB Selects the A/B channel in the dual 12 bit plus exponent mode (INPUT_MODE=3). If
SEL_AB is 0, then the samples with their A/B flag low are used. If SEL_AB is high,
then the samples with their A/B flag high are used.
INPUT_MODE Selects the input format: 0 is the 14 bit input mode, 1 is the 16 bit input mode, 2 is
the 12 bit plus exponent mode, and 3 is the dual 12 bit plus exponent mode.
Unused
MSB_POL Invert the MSB polarity. This will convert an offset binary formatted input to 2's
complement format.
COARSE
after the CIC but before rounding to 20 bits to
- 40 -
DATA SHEET REV 1.0
is
0
is multiplied
0
August 27, 2001