Pentek 6230 Operating Manual page 127

GC4016 MULTI-STANDARD QUAD DDC CHIP
The 12 bit filter coefficients are stored in a 256 word
memory which can be divided into one, two, or four equal
blocks. This allows the user to store one symmetric filter of
up to 512 taps, two symmetric filters of up to 256 taps each,
or four symmetric filters of up to 128 taps each. The number
of filters is set by NFILTER in address 16 of the resampler
control page. The filter used by each channel is selected
using the FILTER_SEL controls in address 18 of the
resampler control page. The filter lengths are cut in half if the
filters are not symmetric. The coefficients are stored in
memory with h stored in the lowest address, where h
0
coefficient multiplied by the newest piece of data. The center
tap of a symmetric filter is h
multiple filters (NFILTER>1), are interleaved in the 256 word
memory.
3.5.3 Restrictions on NMULT
The user does not directly set the value of NDELAY. The
chip sets the value of NDELAY using NO_SYM_RES,
NMULT and NFILTER according to:
=
Floor_2 256
NDELAY
where the function FLOOR_2[X] means the power of two
value that is equal to or less than "X". Since NMULT is
restricted to be greater than or equal to 6 and less than or
equal to 64, then NDELAY is either 4, 8, 16, 32 or 64. The
length of the filter is then:
(
QTAP = NDELAY
The value of NMULT determines both the length of the
filter and the number of delays in the resampling operation.
In general one would choose the largest value of NMULT
which gives an adequately large value of NDELAY. The
choice of NMULT, however, must meet several restrictions.
NMULT must be greater than a minimum, it cannot exceed
the available number of multiplier cycles, and it must be less
than the input delay line segment size. These restrictions are
described below.
The minimum value of NMULT is determined by the
minimum number of clock cycles required to update the
resampler's state. This is a hardware restriction imposed by
the chip's architecture. This limitation is:
≥
NMULT 6 if there are two or more outputs
≥
NMULT 7 if there is only one output
NMULT is the number of complex multiplier operations
required to compute an output sample. Since the resampler
can perform two multiplies every clock cycle, the value of
NMULT cannot exceed two times the number of clock cycles
© GRAYCHIP,INC.
This document contains information which may be changed at any time without notice
is the
0
. The coefficients for
(QTAP/2)-1
( )
[ ]
2 NO_SYM_RES –
----------------------------------------------
( ) ( )
NMULT NFILTER
) NMULT ( )
available to the resampler for each channel. The number of
clock cycles available to the resampler is equal to the clock
rate to the chip divided by the sum of the output sample rates
for each resampler channel. Hence, NMULT must satisfy:
NMULT
Note that the resampler's output sample rate is usually
much less than the clock rate, so that NMULT is rarely limited
by this restriction. NOTE: THE NUMBER OF CLOCK
CYCLES AVAILABLE TO THE RESAMPLER IS REDUCED
BY THE CLOCK DIVIDER DISCUSSED IN THE NEXT
SECTION.
The value of NMULT must also be less than the size of
the delay line formed by the input buffer. The size of the delay
line is either 16 for four resampler channels, 32 for two
channels or 64 for a single channel as set by the NCHAN
control in address 16 of the resampler control page. This
limits NMULT to be less than or equal to 15, 31 or 63
dependent upon the number of resampler channels
The typical resampler configuration will have four active
channels, all using the same filter and the same resampling
ratios. The typical configuration has NCHAN set to 4,
NFILTER set to 1, NMULT set to 15 and NO_SYM_RES set
to 0. This sets NDELAY to 32 and QTAPS to 480. See
Section 7.7.
3.5.4 The Resampler Clock Divider
The resampler has a clock divider that can be used to
reduce power consumption and to slow the calculation rate
of the resampler. The clock divider divides the internal clock
by factors of one to 256 using the RES_CLK_DIV control in
address 22 of the resampler control page. The clock divider
reduces the resampler's computational throughput, so care
must be taken not to reduce the clock rate to the point that
the computations can not be completed on time.
3.5.5 Final Shift and Round
The gain of each resampler output is adjusted by an
up-shift by 0-15 bits (FINAL_SHIFT). This up-shift is applied
just before rounding to the 12, 16, 20 or 24 MSBs (ROUND).
The values of FINAL_SHIFT and ROUND are set in control
register 19 of the resampler control page. The resampler
1. NOTE: If the resampler is being used at much less than its maximum
capacity, i.e., NMULT is much less than twice the number of clock cycles
available (See also RES_CLK_DIV), AND the channels are synchronous, then
NMULT may equal the size of the delay line.
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DATA SHEET REV 1.0
F
≤ × CK
2 ------------------------------------------------------------
∑
(
OUTPUT RATES
August 27, 2001
)
1
.