Pentek 6230 Operating Manual page 7

Pentek Model 62 30/ 6231 O pera t ing M a nu a l
Table of Contents
4.1 Overview..............................................................................................................................................71
4.2 Data Routing and Formats ................................................................................................................71
4.2.1 DDR Bypass Mode, A/D Data, Unpacked (001) ..........................................................72
Table 4−1: Output Data Format − DDR Bypass Mode, Unpacked .........................72
4.2.2 DDR Bypass Mode, A/D Data, Time Packed (010) .....................................................72
Table 4−2: Output Data Format − DDR Bypass Mode, Time Packed ....................72
4.2.3 DDR Bypass Mode, A/D Data, Channel Packed (011) ...............................................73
Table 4−3: Output Data Format − DDR Bypass Mode, Channel Packed ..............73
4.2.4 DDR Mode, 16−Bit, Unpacked I/Q, Tagged (100) .......................................................74
Table 4−4: Output Data Format − DDR Mode, 16−bit, Unpacked I/Q, Tagged ...74
4.2.5 DDR Mode, 24−Bit, Unpacked I/Q, Tagged (101) .......................................................75
Table 4−5: Output Data Format − DDR Mode, 24−bit, Unpacked I/Q, Tagged ...75
4.2.6 DDR Mode, 16−Bit, Packed I/Q (110) ...........................................................................76
Table 4−6: Output Data Format − DDR Mode, 16−bit, Packed I/Q ........................76
4.2.7 DDR Mode, 24−Bit, Packed I/Q (111) ...........................................................................77
Table 4−7: Output Data Format − DDR Mode, 16−bit, Packed I/Q ........................77
5.1 Overview..............................................................................................................................................79
Figure 5−1: Model 6230 Gate/Sync/Clock Logic ..........................................................................79
Figure 5−2: Model 6231 Gate/Sync/Clock Logic ..........................................................................80
5.2 Sync.......................................................................................................................................................80
5.3 Clock .....................................................................................................................................................80
5.4 Gates .....................................................................................................................................................81
Chapter 4: Data Formatting and Routing
Chapter 5: Timing and Synchronization
Pa g e 7
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Rev.: B.4