Pentek 6230 Operating Manual page 210

ADM1024
to be asserted. After masking, the status bits are all OR'd
together to produce the INT output, which will pull low if any
unmasked status bit goes high, i.e., when any measured value
goes out of limit. The ADM1024 also has a dedicated output for
temperature interrupts only, the THERM input/output Pin 2.
The function of this is described later.
The INT output is enabled when Bit 1 of Configuration Register 1
(INT_Enable) is high, and Bit 3 (INT_Clear) is low.
The INT pin has an internal, 100 kΩ pull-up resistor.
VID/IRQ INPUTS
The processor voltage ID inputs VID0 to VID4 can be reconfig-
ured as interrupt inputs by setting Bit 7 of the Channel Mode
Register (address 16h). In this mode they operate as level-triggered
interrupt inputs, with VID0/IRQ0 to VID2/IRQ2 being active
low and VID2/IRQ2 and VID4/IRQ4 being active high. The
individual interrupt inputs can be enabled or masked by setting
VID0/IRQ0
VID1/IRQ1
VID2/IRQ2
VID3/IRQ3
VID4/IRQ4
4
5
CHANNEL
MODE
6
REGISTER
7
6
CONFIGURATION
REGISTER 2
7
HIGH
LIMIT
HIGH
FROM
AND
VALUE
LOW
VALUE
AND LIMIT
LIMIT
REGISTERS
COMPARA-
TORS
LOW
LIMIT
VID0–VID4
REGISTERS
2.5V/EXT.
TEMP 2
0
V
CCP1
1
V
CC
2
+5V
3
INT. TEMP
4
EXT. TEMP1
5
FAN1/AIN1
1 = OUT
6
FAN2/AIN2
OF
7
LIMIT DATA
DEMULTI-
+12V
PLEXER 0
V
CCP2
1
RESERVED
2
RESERVED
3
CI
4
THERM
5
D1 FAULT
6
D2 FAULT
7
16 MASK BITS
INTERRUPT MASK
MASKING
REGISTERS 1 AND 2
DATA
(SAME BIT ORDER AS
FROM BUS
STATUS REGISTERS)
Figure 14. Interrupt Register Structure
or clearing Bits 4 to 6 of the Channel Mode Register and Bits
6 and 7 of Configuration Register 2 (address 4Ah). These interrupt
inputs are not latched in the ADM1024, so they do not require
clearing as do bits in the Status Registers. However, the external
interrupt source should be cleared once the interrupt has been
serviced, or the interrupt request will be reasserted.
INTERRUPT CLEARING
Reading an Interrupt Status Register will output the contents of
the Register, then clear it. It will remain cleared until the moni-
toring cycle updates it, so the next read operation should not be
performed on the register until this has happened, or the result
will be invalid. The time taken for a complete monitoring cycle
is mainly dependent on the time taken to measure the fan speeds,
as described earlier.
The INT output is cleared with the INT_Clear bit, which is Bit
3 of the Configuration Register, without affecting the contents
of the Interrupt (INT) Status Registers.
INTERRUPT
STATUS
REGISTER 1
MASK GATING 11
STATUS
BIT
MASK
BIT
INTERRUPT
STATUS
REGISTER 2
–18–
INT ENABLE INT CLEAR
CONFIGURATION
REGISTER 1
THERM
CLEAR
THERM
INT
THERM
REV. A