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Pentek 6230 Operating Manual

32/16?channel digital receiver vim module for pentek vim baseboards
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Pentek Model 6230/6231 Operating Manual
P age 1
OPERATING MANUAL
MODEL 6230/6231
32/16−Channel Digital Receiver VIM Module
for Pentek VIM Baseboards
Pentek, Inc.
One Park Way
Upper Saddle River, NJ 07458
(201) 818−5900
http://www.pentek.com
Copyright © 2006
Manual Part No: 800.62300
Rev: C.1 − October 23, 2006

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  • Page 1 Pentek Model 6230/6231 Operating Manual P age 1 OPERATING MANUAL MODEL 6230/6231 32/16−Channel Digital Receiver VIM Module for Pentek VIM Baseboards Pentek, Inc. One Park Way Upper Saddle River, NJ 07458 (201) 818−5900 http://www.pentek.com Copyright © 2006 Manual Part No: 800.62300...

  • Page 2: Model

    The obligation of Pentek arising from a warranty claim shall be limited to repairing or at its option, replacing without charge, any product that in Pentek’s sole opinion proves to be defective within the scope of the warranty. Pentek must be notified in writing of the defect or nonconformity within the warranty period and the affected product returned to Pentek within thirty days after discovery of such defect or nonconformity.

  • Page 3: Table Of Contents

    Pentek Model 62 30/ 6231 O pera t ing M a nu a l Pa g e 3 Table of Contents Page Chapter 1: Introduction General Description..........................9 Features ..............................9 Analog/Digital Conversion ......................10 Digital Receivers ..........................10 Digital Interfaces..........................10 Timing and Synchronization......................11 Interrupts .............................11...
  • Page 4 Page 4 Pentek Mo d el 6230/6231 Oper a ting Ma nu al Table of Contents Page Chapter 2: Installation and Connections (continued) Installing the Model 6230/6231 on a VIM Baseboard..............25 Figure 2−4: Typical VIM Baseboard − Connectors & Mounting Holes ......... 26 2.3.1...
  • Page 5 Pentek Model 62 30/ 6231 O pera t ing M a nu a l Pa g e 5 Table of Contents Page Chapter 3: Memory Maps and Register Descriptions Overview..............................41 Model 6230/6231 Memory Map.......................41 Table 3−1: VIM Base Addresses for Models 4290 to 4295 VIM Baseboards ......41 Table 3−2: VIM Base Addresses for Model 4205 VIM Baseboards .........41...
  • Page 6 Page 6 Pentek Mo d el 6230/6231 Oper a ting Ma nu al Table of Contents Page Chapter 3: Memory Maps and Register Descriptions 3.10.4 GATE DISBL ........................54 3.10.5 GATE SRC ......................... 54 3.10.6 TRIG CLEAR ........................54 3.10.7 HOLD MODE ........................
  • Page 7 Pentek Model 62 30/ 6231 O pera t ing M a nu a l Pa g e 7 Table of Contents Page Chapter 4: Data Formatting and Routing Overview..............................71 Data Routing and Formats ........................71 4.2.1 DDR Bypass Mode, A/D Data, Unpacked (001) ............72 Table 4−1: Output Data Format −...
  • Page 8 Page 8 Pentek Mo d el 6230/6231 Oper a ting Ma nu al Table of Contents Page Appendix A: Configuration EEPROM Format Introduction .............................A−1 EEPROM Format Example ......................A−1 Table A−1: VIM ID EEPROM Register..................A−1 Table A−2: EEPROM Example (Model 6230 shown)...............A−2 Appendix B: Analog Devices AD6644 A/D Converter Introduction .............................

  • Page 9: Chapter 1: Introduction

    The Models 6230 and 6231 are general purpose, narrowband digital receiver VIM (Velocity Interface Mezzanine) modules that perform frequency down conversion, low−pass filtering, and decimation of the digitized input signal. The Model 6230 is a 32−channel VIM−4 module that features four 14−bit, 65−MHz A/D converters, and can be configured with up to 32 channels of narrowband receivers.

  • Page 10: Analog/Digital Conversion

    Pentek Mo d el 6230/6231 Oper a ting Ma nu al Analog/Digital Conversion The Model 6230 [Model 6231] accepts four [two] analog RF inputs on front panel SMA connectors in the range of DC to 90 MHz to support direct IF undersampling. Each input signal is buffered by an Analog Devices OPA642 amplifier.

  • Page 11: Timing And Synchronization

    LVDS (low−voltage differential signal) sync bus. This sync bus includes sample clock, gate, and sync signals. It allows one Model 6230/6231 to act as a bus Master, driving these signals out to a front panel flat cable using LVDS differential signaling. Addi−...

  • Page 12: Block Diagrams

    Page 12 Pentek Mo d el 6230/6231 Oper a ting Ma nu al Block Diagrams The following are block diagrams of the Models 6230 and 6231 digital receivers. RF In RF In RF In RF In Sample Clock In AMPLIFIER...

  • Page 13: Figure 1−3: Model 6230 Block Diagram, With Option 105

    Pentek Model 62 30/ 6231 O pera t ing M a nu a l Pa g e 1 3 Block Diagrams (continued) The following are block diagrams of the Models 6230 and 6231 with Option 105. Sample RF In RF In...

  • Page 14: Channels

    VIM baseboard. These are identified as Processors A, B, C, and D for the 6230 [Processors A and B, or C and D, for the 6231, depending on the mezzanine position that the module is installed into on the VIM baseboard].

  • Page 15: Fpga Configuration

    AD6644 or GC4016 output data. Pentek offers this capability as a sepa− rate development package, Model 4953 − Option 230 for the 6230, or Model 4953 − Option 231 for the Model 6231. Contact Pentek at (201) 818−5900 for details about this package.

  • Page 16: Model 6230

    I/O pins. See Section 3.22 for description of this I/O register. When the Model 6230 is attached to a Pentek VIM baseboard, the FPGAs provide serial port connectivity as shown in the following illustration. Virtex−E FPGA 1 Virtex−E FPGA 2...

  • Page 17: Model 6231

    Pentek Model 62 30/ 6231 O pera t ing M a nu a l Pa g e 1 7 1.10 FPGA Configuration (continued) 1.10.2 Model 6231 All spare pins on the Model 6231 FPGA are brought to the front panel FPGA...

  • Page 18: Specifications

    Page 18 Pentek Mo d el 6230/6231 Oper a ting Ma nu al 1.12 Specifications Front Panel Connectors Analog Inputs: Four [two] female SMA connectors (one per A/D converter) Sample Clock Input: One female SMA connector Sync/Gate Bus: One 26−pin connector, with four gates, one sync, and one...
  • Page 19 Pentek Model 62 30/ 6231 O pera t ing M a nu a l Pa g e 1 9 1.12 Specifications (continued) Analog/Digital Converters Quantity: Four [two] (enclosed in a shielded cover) Device: Analog Devices AD6644 (see Appendix Sampling Rate:...
  • Page 20 Page 20 Pentek Model 6230/6231 Operating Manual 1.12 Specifications (continued) Field−Programmable Gate Arrays Quantity: Two [one], one for Processors A & B, one for Processors C & D Device: Xilinx Virtex−E XCV300E (standard); Option 600 – Xilinx Virtex−E XCV600E Programming:...

  • Page 21: Chapter 2: Installation And Connections

    Please save the shipping container and packing material in case reshipment is required. Jumper Block Settings The Model 6230 [Model 6231] PCB has ten [six] jumper blocks that the user can set. With Option 105, the PCB has only two jumper blocks. These jumpers are described in the following subsections.

  • Page 22: Fpga Configuration Data Source Jumper

    Page 22 Pentek Mo d el 6230/6231 Oper a ting Ma nu al Jumper Block Settings (continued) 2.2.2 FPGA Configuration Data Source Jumper Jumper JB9 selects the source of the Virtex FPGA configuration data down− load. The FPGA can select its configuration data either from an on−board Serial EEPROM or from a serial download (X−Checker cable), depending on...

  • Page 23: Figure 2−1: Model 6230 Pcb Assembly, Component Side

    Pentek Model 62 30/ 6231 O pera t ing M a nu a l Pa g e 2 3 Jumper Block Settings (continued) Upper Front Panel JB10 Rear Mounting Holes Filter Bypass Jumpers Shield removed Figure 2−1: Model 6230 PCB Assembly, Component Side...

  • Page 24: Figure 2−2: Model 6231 Pcb Assembly, Component Side

    Page 24 Pentek Mo d el 6230/6231 Oper a ting Ma nu al Jumper Block Settings (continued) Front Panel JB10 JB10 Rear Mounting Hole Filter Bypass Jumpers Shield removed Figure 2−2: Model 6231 PCB Assembly, Component Side Panel Mounting Holes...

  • Page 25: Installing The Model 6230/6231 On A Vim Baseboard

    Model 6231 VIM−2 module on a VIM−compatible baseboard. Pentek’s VIM base− boards ship with two blank panels and four VIM interface connectors where you can install optional VIM modules, such as the Model 6230 or Model 6231. An illustration of a typical Pentek VIM baseboard is provided in Figure 2−4...

  • Page 26: Figure 2−4: Typical Vim Baseboard − Connectors & Mounting Holes

    Page 26 Pentek Mo d el 6230/6231 Oper a ting Ma nu al Installing the Model 6230/6231 on a VIM Baseboard (continued) Top Position VIM Connectors Top Position Mounting Holes Bottom Position VIM Connectors Bottom Position Mounting Holes Figure 2−4: Typical VIM Baseboard − Connectors & Mounting Holes...

  • Page 27: Installing Model 6230, Or Model 6231 Without Option 102

    (The shipping brackets may be discarded, or saved to store the panels on the VIM module if it is removed from the VIM baseboard.) 3) At the rear of the Model 6230 PCB, on the component side, are two nylon spacers [one spacer on the Model 6231 VIM−2 PCB] (see Figure 2−6...

  • Page 28: Figure 2−6: Vim Module Nylon Spacer

    2−2). If either spacer is in the front hole, reposition it using the nylon screw on the solder side of the module. 4) For the Model 6230, remove both blank panel inserts from the VIM baseboard, by removing the two countersunk Phillips screws from each insert (see illustration below).
  • Page 29 Pentek Model 62 30/ 6231 O pera t ing M a nu a l Pa g e 2 9 Installing the Model 6230/6231 on a VIM Baseboard (continued) 2.3.1 Installing Model 6230, or Model 6231 w/o Option 102 (continued) 5) With the VIM baseboard’s component side (the side with the VIM connectors) facing up, align the four VIM connectors on the Model 6230 VIM−4 module (J1, J2, J3, and J4) with the four VIM connectors on the...
  • Page 30 Page 30 Pentek Mo d el 6230/6231 Oper a ting Ma nu al Installing the Model 6230/6231 on a VIM Baseboard (continued) 2.3.2 Installing Model 6231 with Option 102 The Model 6231 with Option 102 is shipped as an assembled unit and must be disassembled for installation on your baseboard.

  • Page 31: Figure 2−9: Vim Module Nylon Spacer

    Pentek Model 62 30/ 6231 O pera t ing M a nu a l Pa g e 3 1 Installing the Model 6230/6231 on a VIM Baseboard (continued) 2.3.2 Installing Model 6231 with Option 102 (continued) 6) A nylon spacer is installed on the component side of the Model 6231 PCB, between the VIM connectors.

  • Page 32: Installing Model 6231 With Option 102

    Page 32 Pentek Mo d el 6230/6231 Oper a ting Ma nu al Installing the Model 6230/6231 on a VIM Baseboard (continued) 2.3.2 Installing Model 6231 with Option 102 (continued) 8) With the VIM baseboard’s component side (the side with the VIM connectors) facing up, align the two VIM connectors on the Model 6231 VIM−2 module (J1 and J2) with two VIM connectors on the baseboard—...

  • Page 33: Figure 2−12: Vim Baseboard With Option 102 Front Panel Assembly

    Pentek Model 62 30/ 6231 O pera t ing M a nu a l Pa g e 3 3 Installing the Model 6230/6231 on a VIM Baseboard (continued) 2.3.2 Installing Model 6231 with Option 102 (continued) 13) Install the Option 102 front panel assembly, which is in two pieces depending on which blank panel you removed in the prior step, onto the VIM baseboard front panel, using the four long pan−head Phillips screws...

  • Page 34: Figure 2−14: Option 102 Pcb Mounted On Vim Module

    Page 34 Pentek Mo d el 6230/6231 Oper a ting Ma nu al Installing the Model 6230/6231 on a VIM Baseboard (continued) 2.3.2 Installing Model 6231 with Option 102 (continued) 15) Align the Option 102 PCB connectors J1 and J2 with the two stacking connectors on the VIM module.

  • Page 35: Front Panel Connections

    Pa g e 3 5 Front Panel Connections The Model 6230 has two (upper and lower) VIM front panels. The Model 6231 stan− dard configuration has a single VIM front panel—a second front panel is provided with Option 102, mounted on an adjacent board. The Model 6231 panels can be installed in...

  • Page 36: Figure 2−15: Models 6230 And 6231 Front Panels

    Page 36 Pentek Mo d el 6230/6231 Oper a ting Ma nu al Front Panel Connections (continued) Upper Panel Lower Standard Option 102 Panel Panel Panel Model 6231 Model 6230 Figure 2−15: Models 6230 and 6231 Front Panels Rev.: B.4...

  • Page 37: Sync/Gate Connector

    When the Model 6230/6231 is a sync bus Master, these pins out− put the bus to other slave units. When the 6230/6231 is a Slave, these pins input the signals from a Master. This connector also accepts two TTL gate and sync inputs.

  • Page 38: Fpga Connector

    Front Panel Connections (continued) 2.4.5 FPGA Connector The 50−pin FPGA connector for the Model 6230 includes two 16−pin FPGA input/output data paths. The pins correspond to bits D15 through D0 of the I/O Data Register for each of the FPGAs (see Section 3.22).

  • Page 39: Front Panel Leds

    Pentek Model 62 30/ 6231 O pera t ing M a nu a l Pa g e 3 9 Front Panel LEDs The Model 6230 front panel has eight LED indicators [six LEDs on the Model 6231], as illustrated in Figure 2−15, on...
  • Page 40 Page 40 Pentek Mo d el 6230/6231 Oper a ting Ma nu al This page is intentionally blank Rev.: B.4...

  • Page 41: Chapter 3: Memory Maps And Register Descriptions

    Chapter 3: Memory Maps and Register Descriptions Overview This chapter describes processor access to the Model 6230 and Model 6231 from the VIM baseboard. Memory maps to VIM module resources are given from the baseboard processor’s viewpoint, and details are provided describing the use of each resource.

  • Page 42: Table 3−3: Model 6230/6231 Memory Map

    Pentek Mo d el 6230/6231 Oper a ting Ma nu al Model 6230/6231 Memory Map (continued) The following table provides a memory map for accessing the Model 6230/6231 control registers. All register addresses are expressed as offsets from the VIM base address for the applicable VIM baseboard—see Table 3−1...

  • Page 43: Virtex Config Register

    Pentek Model 62 30/ 6231 O pera t ing M a nu a l Pa g e 4 3 Virtex Config Register The Virtex Config Register is used to reconfigure/reprogram the Virtex FPGAs. The bits in this register allow you to read and set the status of the FPGA configuration cycle, and to upload the configuration from a VIM processor.

  • Page 44: Done

    Page 44 Pentek Mo d el 6230/6231 Oper a ting Ma nu al Virtex Config Register (continued) 3.3.4 DONE Bit D02 This read−only bit indicates the status of the Virtex FPGA’s ‘DONE’ pin. When read as logic '0', the FPGA is in the configuration cycle. When read as logic '1', the FPGA has completed configuration.

  • Page 45: Wait States Register

    The wait states are equal to the greater of the VIM interface minimum write cycle time or the wait state selection in this register. For Model 6230/6231 boards with a DBCLK of 50 MHz or less, a setting of GC DDR = 0x2 and CTL REG = 0x2 is adequate.

  • Page 46: Hardware Monitor Port Register

    PCB. There are four tem− perature sensors on the Model 6230 [two on the Model 6231], which are controlled by the Hardware Monitor Port. When an over−temperature or over−voltage condition is indicated, the red TEMP LED is illuminated on the front panel.

  • Page 47: Table 3−8: Adm1024 Registers

    • On the Model 6230 with two ADM1024’s, the bus addresses are ("Upper" and “Lower” refer to the associated VIM position on the baseboard for each ADM1024): Upper ADM1024 −...

  • Page 48: Master Control Register

    Pentek Mo d el 6230/6231 Oper a ting Ma nu al Master Control Register The Master Control Register allows you to configure the Model 6230 or Model 6231 as a Master or Slave on the LVDS sync bus, toggle the on−board sync bus termination, select the source of the clock, select a clock divider, select the source and polarity of the sync, and enable the on−board oscillator.

  • Page 49: Sync Pol

    EXT SYNC EN Bit D07 When this Model 6230/6231 is the sync bus Master (MASTR bit D00 = 1) or when the LVDS sync bus sync input is bypassed (SYNC SRC bit D09 = 0), this bit selects the sync signal for the GC4016 DDRs from either an on−board register or the external TTL sync input.

  • Page 50: Ext Clk

    EXT CLK Bit D02 When this Model 6230/6231 is a sync bus Master (MASTR bit D00 = 1) or when the sync bus clock is bypassed (CLK SRC bit D04 = 0), this bit selects the module’s clock signal from either the on−board oscillator or the external clock input.

  • Page 51: Bypass Rate Divide Register

    Pentek Model 62 30/ 6231 O pera t ing M a nu a l Pa g e 5 1 Bypass Rate Divide Register This register sets the decimation rate of data samples written to the processor BIFO when the module is in DDR Bypass mode (see Section 4.2, Data Routing and Formats).

  • Page 52: Channel Enable Register

    Page 52 Pentek Mo d el 6230/6231 Oper a ting Ma nu al Channel Enable Register The Channel Enable Register enables the output from any of the eight receiver channels of the two GC4016s associated with a VIM baseboard processor, to a processor’s BIFO.

  • Page 53: Gate Control Register

    Gates B and D from Processor B (or Processor D). When the sync bus is bypassed (GATE SRC bit D04 = 0), the Model 6230/6231 gener− ates only Gate A and B for selection on the board. Refer to...

  • Page 54: Gate Pol

    Page 54 Pentek Mo d el 6230/6231 Oper a ting Ma nu al 3.10 Gate Control Register (continued) 3.10.2 GATE POL Bit D08 This bit selects the polarity of the external TTL gate/trigger input. This bit is only available to Processors A and C (Processor A controls polarity for B;...

  • Page 55: Hold Mode

    Pentek Model 62 30/ 6231 O pera t ing M a nu a l Pa g e 5 5 3.10 Gate Control Register (continued) 3.10.7 HOLD MODE Bit D02 This bit enables a gate Hold after the trigger is received in Trigger mode (GATE/TRIG bit D01 = 1, below).

  • Page 56: Trigger Length Register

    Page 56 Pentek Mo d el 6230/6231 Oper a ting Ma nu al 3.11 Trigger Length Register When Trigger mode is selected for a BIFO gate (GATE/TRIG = 1, Gate Control Regis− ter, Section 3.10.8), this register sets the length that the gate is active (BIFO writes enabled) after receipt of the trigger.

  • Page 57: Channel Control Register

    Pentek Model 62 30/ 6231 O pera t ing M a nu a l Pa g e 5 7 3.12 Channel Control Register The Channel Control Register selects the data routing mode of each processor channel, and contains bits to reset the data formatter state machine (in the associated FPGA), to enable the sync signal to reset the DDR Bypass mode decimate dividers, and to reset the processor channel.

  • Page 58: Dat Moden

    Page 58 Pentek Mo d el 6230/6231 Oper a ting Ma nu al 3.12 Channel Control Register (continued) 3.12.4 DAT MODEn Bits D02 to D00 These three bits select the data routing mode from the two GC4016 DDRs to the FPGA associated with this processor channel (for example, FPGA1 for Processor A).

  • Page 59: Sync/Gate Generator Register

    Pa g e 5 9 3.13 Sync/Gate Generator Register The Sync/Gate Generator Register is used on a Model 6230/6231 that is configured as a sync bus Master (MASTR = 1, Master Control Register, Section 3.7.10), or on a board that is not connected to an external LVDS sync bus.

  • Page 60: Interrupt Mask Register

    Page 60 Pentek Mo d el 6230/6231 Oper a ting Ma nu al 3.14 Interrupt Mask Register The Interrupt Mask Register contains one enable bit for each interrupt condition defined for the controlling processor. Each processor on the VIM baseboard has its own version of this register.

  • Page 61: Table 3−18: Interrupt Register Bits

    Pentek Model 62 30/ 6231 O pera t ing M a nu a l Pa g e 6 1 3.14 Interrupt Mask Register (continued) Table 3−18: Interrupt Register Bits Bit Name Bit Position Interrupt Function Each of these bits is associated with a Temperature/Voltage sensor interrupt for part of the Model 6230/6231.

  • Page 62: Interrupt Flag Register

    Page 62 Pentek Mo d el 6230/6231 Oper a ting Ma nu al 3.15 Interrupt Flag Register The Interrupt Flag Register has one read/clear bit associated with each interrupt con− dition for the VIM processor (the same bit associations as the Interrupt Mask Register, Section 3.14).

  • Page 63: Interrupt Status Register

    Pentek Model 62 30/ 6231 O pera t ing M a nu a l Pa g e 6 3 3.16 Interrupt Status Register The Interrupt Status Register has one read−only bit associated with each interrupt con− dition for the VIM processor (the same bit associations as the Interrupt Mask Register, Section 3.14).

  • Page 64: Semaphore Register

    Page 64 Pentek Mo d el 6230/6231 Oper a ting Ma nu al 3.17 Semaphore Register The Semaphore Register contains communications bits that may be written by one pro− cessor on the VIM baseboard and read by all four processors [two processors for the Model 6231].

  • Page 65: I/O Direction 2 Register (Model 6231 Only)

    Pentek Model 62 30/ 6231 O pera t ing M a nu a l Pa g e 6 5 3.18 I/O Direction 2 Register (Model 6231 only) The I/O Direction 2 Register determines the input/output direction of each bit in the FPGA I/O Data 2 Register, Section 3.19...

  • Page 66: I/O Data 2 Register (Model 6231 Only)

    Page 66 Pentek Mo d el 6230/6231 Oper a ting Ma nu al 3.19 I/O Data 2 Register (Model 6231 only) The I/O Data 2 Register allows you to read or write data from the Virtex FPGA to the front panel FPGA connector (Section 2.4.5).

  • Page 67: I/O Direction Register

    Processor A and Processor C on the VIM baseboard have their own version of this register, for the FPGA associated with that processor. This register is available on the Model 6230 and only with Option 102 on the Model 6231.

  • Page 68: I/O Enable Register

    C on the VIM baseboard have their own version of this register, for the FPGA associated with that processor (for example, FPGA1 for Processor A). This register is available on the Model 6230 and only with Option 102 on the Model 6231.

  • Page 69: I/O Data Register

    FPGA associated with that processor (for example, FPGA1 for Processor A). This register is available on the Model 6230 and only with Option 102 on the Model 6231. The following table shows which bit in this register is associated with each connector data bit.

  • Page 70: Graychip 0 & 1 Registers

    The Graychip Registers allow you to read or write data from/to each Graychip GC4016 DDR. There are eight sets of registers on the Model 6230 [four sets on the Model 6231], one for each GC4016 on the module, with 128 registers in each set. Each processor on the VIM baseboard can use two sets of registers, for the two GC4016 DDRs associated with that processor.

  • Page 71: Chapter 4: Data Formatting And Routing

    Pentek Model 62 30/ 6231 O pera t ing M a nu a l Pa g e 7 1 Chapter 4: Data Formatting and Routing Overview This chapter provides descriptions of the data routing and formatting for the Model 6230/6231.

  • Page 72: Ddr Bypass Mode, A/D Data, Unpacked (001)

    Page 72 Pentek Mo d el 6230/6231 Oper a ting Ma nu al Data Routing and Formats (continued) 4.2.1 DDR Bypass Mode, A/D Data, Unpacked (001) This mode takes the raw 14−bit data directly from the two A/Ds, bypassing the GC4016 DDRs. The output is written to the VIM BIFO at a programmed decimation rate N, where N is 1 to 4096, only when the gate is enabled.

  • Page 73: Ddr Bypass Mode, A/D Data, Channel Packed (011)

    Pentek Model 62 30/ 6231 O pera t ing M a nu a l Pa g e 7 3 Data Routing and Formats (continued) 4.2.3 DDR Bypass Mode, A/D Data, Channel Packed (011) This mode takes the raw 14−bit data directly from the two A/Ds, bypassing the GC4016 DDRs.

  • Page 74: Ddr Mode, 16−Bit, Unpacked I/Q, Tagged (100)

    Page 74 Pentek Mo d el 6230/6231 Oper a ting Ma nu al Data Routing and Formats (continued) 4.2.4 DDR Mode, 16−Bit, Unpacked I/Q, Tagged (100) This mode expects data from the two GC4016 DDRs to be 32−bit I/Q pairs.

  • Page 75: Ddr Mode, 24−Bit, Unpacked I/Q, Tagged (101)

    Pentek Model 62 30/ 6231 O pera t ing M a nu a l Pa g e 7 5 Data Routing and Formats (continued) 4.2.5 DDR Mode, 24−Bit, Unpacked I/Q, Tagged (101) This mode expects data from the two GC4016 DDRs to be 48−bit I/Q pairs.

  • Page 76: Ddr Mode, 16−Bit, Packed I/Q (110)

    Page 76 Pentek Mo d el 6230/6231 Oper a ting Ma nu al Data Routing and Formats (continued) 4.2.6 DDR Mode, 16−Bit, Packed I/Q (110) This mode expects data from the two GC4016 DDRs to be 32−bit I/Q pairs. Data is accepted and multiplexed to the VIM BIFO in a scanned manner starting with the first of the eight receiver channels.

  • Page 77: Ddr Mode, 24−Bit, Packed I/Q (111)

    Pentek Model 62 30/ 6231 O pera t ing M a nu a l Pa g e 7 7 Data Routing and Formats (continued) 4.2.7 DDR Mode, 24−Bit, Packed I/Q (111) This mode expects data from the two GC4016 DDRs to be 48−bit I/Q pairs.
  • Page 78 Page 78 Pentek Mo d el 6230/6231 Oper a ting Ma nu al This page is intentionally blank Rev.: B.4...

  • Page 79: Chapter 5: Timing And Synchronization

    LVDS sync bus if the board is a bus Master, or come in on the LVDS sync bus for a bus Slave unit. The Model 6230/6231 may, alternately, bypass the sync bus and use its own gate, sync, or clock sources for timing and control.

  • Page 80: Sync

    2.4.4), or a sync signal can be generated by a register write by each processor (Section 3.13). When the Model 6230/6231 is a sync bus Master, the gener− ated sync is output to the LVDS Sync Bus. Clock The clock for all the board functions can be driven from either the front panel LVDS...

  • Page 81: Gates

    When the Model 6230/6231 is a sync bus Master, the generated gates are output to the LVDS Sync Bus. When the Model 6231 is a Master, the board generates four gates for...
  • Page 82 Page 82 Pentek Mo d el 6230/6231 Oper a ting Ma nu al This page is intentionally blank Rev.: B.4...

  • Page 83: A.1 Introduction

    EEPROM Format Example Table A−2 on the next page shows the contents of the ID EEPROM for the Model 6230, and an explanation of what each pair of 16−bit words is used for. The SDRAM location is the address where each pair of words is stored relative to the start address of the Global SDRAM on the VIM baseboard.

  • Page 84: Table A−2: Eeprom Example (Model 6230 Shown)

    Page A−2 Pentek Mo d el 6230/6231 Oper a ting Ma nu al EEPROM Format Example (continued) Table A−2: EEPROM Example (Model 6230 shown) EEPROM SDRAM Contents Comments Word Location Location 00/01 +0x00 0x00EE C0DE Valid data flag 02/03 +0x04...

  • Page 85: B.1 Introduction

    P e nte k M o d e l 6 2 3 0 / 6 23 1 O p e r a t in g M a nu a l Pa g e B − 1 Appendix B: Analog Devices AD6644 A/D Converter Introduction The following pages are a reprint of the Analog Devices AD6644 14−Bit, 65 MHz A/D Converter data sheet.
  • Page 86 Page B−2 Pentek Mo d el 6230/6231 Oper a ting Ma nu al Thi s p age is i nten tio na lly b lan k Rev.: B.4...
  • Page 87 14-Bit, 40 MSPS/65 MSPS A/D Converter AD6644 FEATURES Designed for multichannel, multimode receivers, the AD6644 is 65 MSPS Guaranteed Sample Rate part of ADI’s new SoftCell™ transceiver chipset. The AD6644 40 MSPS Version Available achieves 100 dB multitone, spurious-free dynamic range (SFDR) Sampling Jitter <...
  • Page 88 AD6644–SPECIFICATIONS DC SPECIFICATIONS = 5 V, DV = 3.3 V; T = –25 C, T = +85 C) Test AD6644AST-40 AD6644AST-65 Parameter Temp Level Unit RESOLUTION Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full –10 –10 Gain Error Full –10 –6...
  • Page 89 AD6644 AC SPECIFICATIONS = 3.3 V; ENCODE and ENCODE = Maximum Conversion Rate MSPS; T = 5 V, DV = –25 C, T = +85 C) Test AD6644AST-40 AD6644AST-65 Parameter Temp Level Unit Analog Input 2.2 MHz 25°C 74.5 74.5 @ –1 dBFS 15.5 MHz 25°C...
  • Page 90 AD6644–SPECIFICATIONS Test AD6644AST-40/65 Parameter Name Temp Level Unit DATA READY (DRY )/DATA, OVR Data Ready to DATA Delay (Hold Time) Note 6 H_DR Encode = 65 MSPS (50% Duty Cycle) Full Encode = 40 MSPS (50% Duty Cycle) Full 12.8 13.4 14.2 Data Ready to DATA Delay (Setup Time)
  • Page 91 AD6644 ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS Test Level Parameter Unit 100% production tested. 100% production tested at 25°C, and guaranteed by ELECTRICAL design and characterization at temperature extremes. Voltage Voltage III Sample tested only. Analog Input Voltage IV Parameter is guaranteed by design and characterization Analog Input Current testing.
  • Page 92 AD6644 PIN FUNCTION DESCRIPTIONS Pin No. Name Function 1, 33, 43 3.3 V Power Supply (Digital) Output Stage Only. 2, 4, 7, 10, 13, 15, 17, 19, 21, 23, Ground. 25, 27, 29, 34, 42 2.4 V (Analog Reference). Bypass to ground with 0.1 µF microwave chip capacitor.
  • Page 93 AD6644 DEFINITIONS OF SPECIFICATIONS Minimum Conversion Rate Analog Bandwidth The encode rate at which the SNR of the lowest analog signal The analog input frequency at which the spectral power of the frequency drops by no more than 3 dB below the guaranteed limit. fundamental frequency (as determined by the FFT analysis) is Maximum Conversion Rate reduced by 3 dB.
  • Page 94 AD6644 EQUIVALENT CIRCUITS CURRENT MIRROR D0–D13, OVR, DRY Figure 2. Analog Input Stage CURRENT MIRROR Figure 5. Digital Output Stage LOADS ENCODE ENCODE 2.4V 100 A LOADS Figure 3. ENCODE Inputs Figure 6. 2.4 V Reference DMID CURRENT MIRROR C1 OR C2 Figure 4.
  • Page 95 Typical Performance Characteristics– AD6644 75.0 ENCODE = 65MSPS –10 ENCODE = 65MSPS, AIN = –1dBFS AIN = 2.2MHz @ –1dBFS SNR = 74.5dB TEMP = –25 C, 25 C, 85 C –20 74.5 SFDR = 92dBc –30 T = –25 C –40 74.0 –50...
  • Page 96 AD6644 –10 ENCODE = 65MSPS ENCODE = 65MSPS WORST OTHER SPUR AIN = 15MHz, AIN = –1dBFS –20 15.5MHz @ –7dBFS NO DITHER –30 –40 –50 –60 –70 –80 –90 HARMONICS (2 –100 –110 –120 –130 ANALOG FREQUENCY – MHz FREQUENCY –...
  • Page 97 AD6644 ENCODE = 65MSPS ENCODE = 65MSPS –10 –10 AIN = 15.5MHz @ –29.5dBFS AIN = 15.5MHz @ –29.5dBFS NO DITHER DITHER @ –19dBm –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110...
  • Page 98 AD6644 THEORY OF OPERATION 0.1 F T1–4T The AD6644 analog-to-digital converter (ADC) employs a three CLOCK ENCODE SOURCE stage subrange architecture. This design approach achieves the AD6644 required accuracy and speed while maintaining low power and ENCODE small die size. HSMS2812 DIODES As shown in the functional block diagram, the AD6644 has...
  • Page 99 AD6644 tion of high frequency, high resolution design practices. All of In applications where dc-coupling is required, a new differential the digital outputs are segregated to two sides of the chip, with output op amp from Analog Devices, the AD8138, can be used the inputs on the opposite side for isolation purposes.
  • Page 100 AD6644 The Encode signal may be generated using an onboard crystal EVALUATION BOARD The evaluation board for the AD6644 is straightforward, oscillator, U5. The on-board oscillator may be replaced by an external encode source via the SMA connector labeled OPT_CLK containing all required circuitry for evaluating the device.
  • Page 101 AD6644 Figure 30. AD6644ST/PCB Schematic (GS02357D Schematic) REV. 0 –15–...
  • Page 102 AD6644 Figure 31. AD6644ST/PCB Top Side Silkscreen Figure 32. AD6644ST/PCB Top Side Copper REV. 0 –16–...
  • Page 103 AD6644 Figure 33. AD6644ST/PCB Bottom Side Silkscreen Figure 34. AD6644ST/PCB Bottom Side Copper REV. 0 –17–...
  • Page 104 AD6644 Figure 35. AD6644ST/PCB Ground Layer – Layers 2 and 5 (Negative) Figure 36. AD6644ST/PCB “Split” Power Layer – Layers 3 and 4 (Negative) REV. 0 –18–...
  • Page 105 AD6644 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 52-Terminal Plastic Low Profile Quad Flatpack (ST-52) 0.063 (1.60) 0.472 (12.00) SQ 0.030 (0.75) 0.018 (0.45) SEATING PLANE 0.394 TOP VIEW (10.0) (PINS DOWN) 0.006 (0.15) 0.002 (0.05) 0.026 (0.65) 0.015 (0.38) 0.057 (1.45) 0.009 (0.22) 0.053 (1.35)
  • Page 106 Page B−4 Pentek Mo d el 6230/6231 Oper a ting Ma nu al Rev.: B.4...

  • Page 107: C.1 Introduction

    P e nte k M o d e l 6 2 3 0 / 6 23 1 O p e r a t in g M a nu a l Pa ge C− 1 Appendix C: Graychip GC4016 Digital Receiver Introduction The following pages are a reprint of the Graychip GC4016 Quad Narrowband Digital Receiver Data Sheet.
  • Page 108 Page C−2 Pentek Mo d el 6230/6231 Oper a ting Ma nu al Thi s p age is i nten tio na lly b lan k Rev.: B.4...
  • Page 109 SLWS133A GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 August 27, 2001 Graychip reserves the right to make changes in circuit design and/or specifications at any time without notice. The user is cautioned to verify that datasheets are current before placing orders. Information provided by Graychip is believed to be accurate and reliable.
  • Page 110 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 REVISION HISTORY Revision Date Description February 24, 2000 Original April 10, 2000 Rewritten to reflect 2.5volt core, 3.3volt I/O power requirements, Removed all references to TQ100 thin quad flat package, All references to GC4017 are changed to GC4016, Added Vcore and Vpin descriptions throughout, Updated power consumption equations, Simplified AC timing specifications,...
  • Page 111 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 CONTACTING GRAYCHIP CORPORATE OFFICES: GRAYCHIP, Inc. 2185 Park Blvd. Palo Alto, CA 94306 PHONE: (650) 323-2955 FAX: (650) 323-0206 WEB PAGE: www.graychip.com E-MAIL: sales@graychip.com tech-support@graychip.com © GRAYCHIP,INC. - ii - August 27, 2001 This document contains information which may be changed at any time without notice...
  • Page 112 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 Table of Contents KEY FEATURES ......................... 1 BLOCK DIAGRAM ........................1 FUNCTIONAL DESCRIPTION ....................2 CONTROL INTERFACE ............................2 INPUT FORMAT ................................ 4 THE DOWN CONVERTERS ............................. 4 MULTICHANNEL MODES............................10 RESAMPLER................................
  • Page 113 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 LIST OF FIGURES Figure 1: GC4016 Block Diagram ................................. 1 Figure 2: Normal Control I/O Timing ..............................3 Figure 3: Edge Write Control Timing..............................3 Figure 4: The Down Converter Channel ............................... 5 Figure 5: Zero Pad Synchronization..............................

  • Page 114: Key Features

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 KEY FEATURES • 0.02 Hz tuning resolution • >100 dB far band rejection • Input rates up to 100 MSPS • >115 dB spur free dynamic range • Four independent digital down convert (DDC) •...

  • Page 115: Functional Description

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 FUNCTIONAL DESCRIPTION CONTROL INTERFACE The GC4016 quad receiver chip contain four identical The chip is configured by writing control information into down-conversion circuits. Each downconvert circuit accepts control registers within the chip. The control registers are a real sample rate up to 100 MHz, down converts a selected grouped into 8 global registers and 128 pages of registers, carrier frequency to zero, decimates the signal rate by a...

  • Page 116: Figure 2: Normal Control I/O Timing

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 A[0-4] CDLY C[0-7] READ CYCLE- NORMAL MODE CSPW A[0-4] C[0-7] WRITE CYCLE- NORMAL MODE A[0-4] CDLY C[0-7] READ CYCLE- RD HELD LOW CSPW A[0-4] C[0-7] WRITE CYCLE- RD HELD LOW Figure 2. Normal Control I/O Timing processors that do not provide stable data before the start of chip’s expansion bus.

  • Page 117: Input Format

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 THE DOWN CONVERTERS INPUT FORMAT Each down converter contains an NCO and a mixer to The chip accept five input formats: quadrature down convert the signal to baseband, followed by (1) Four input ports of 14 bit data, a 5 stage Cascade Integrate Comb (CIC) filter and two (2) Three input ports of 16 bit data,...

  • Page 118: Figure 4: The Down Converter Channel

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 compensating for the droop in the CIC filter’s passband. The bit word (6 integer bits and 26 fractional bits). The time second stage is a 63 tap decimate by 2 filter (PFIR) with user resolution of the new sampling points is user programmable programmable tap weights.

  • Page 119: Figure 5: Zero Pad Synchronization

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 Sample taken Input Data is sampled every 3+NZERO CLOCKS (NZERO+1) clocks thereafter Figure 5. Zero Pad Synchronization Zero padding lowers the effective decimation ratio. For The tuning frequency is set to FREQ according to the example, the minimum complex output decimation using a formula FREQ = 2 , where F is the desired tuning...

  • Page 120: Figure 7: Example Nco Spurs

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 FREQ=5/24 F FREQ=5/24 F -105 dB -116 dB a) Worst case spectrum without dither b) Spectrum with dither (tuned to same frequency) Figure 7. Example NCO Spurs -107 dB -121 dB a) Plot without dither or phase initialization b) Plot with dither and phase initialization Figure 8.

  • Page 121: Figure 9: Five Stage Cic Decimate By N Filter

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 UPPER 24 BITS 20 BITS DATA 24 BITS DATA CLOCKED AT FULL RATE CLOCKED AT 1/N RATE Figure 9. Five Stage CIC Decimate by N Filter 3.3.5 The First Decimate By Two Filter The CIC filter has a gain equal to N which must be (CFIR)

  • Page 122: Figure 10: Typical Cfir Specifications

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 Signal of Interest Passband (Typically 0.05 to 0.125 F CFIR 0 dB Very wide transition band Power Stopband (Typically starts at 0.375 F CFIR -100 dB Frequency CFIR CFIR CFIR Figure 10. Typical CFIR Specifications the decimate by two phasing in order to generate the filter if the sum of the 63 coefficients is equal to 65536.

  • Page 123: Multichannel Modes

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 to determine when a new fine gain setting takes effect. It is combining two channels using the SPLITIQ mode. Four normally set to take effect immediately, but can be used to channels may be combined to provide 3 to 4 times the single synchronize the gain changes between multiple channels in channel output bandwidth (with reduced out of band...
  • Page 124 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 Double rate real output can be generated by combining one channel while the imaginary portion (Q ) is processed SPLITIQ and complex to real conversion. The complex to in the next channel. Channels A and B are described here, real signal processing is the same as described in Section channels C and D can be combined as well.

  • Page 125: Resampler

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 Table 2: Multichannel mode settings Input Real Complex Output Two 2X output channels Single 4x output channel Rate Output Complex Real Complex Real Complex Real Complex Real Format Channel SPLITIQ PHASE 90 0 90 0 90 0...

  • Page 126: Figure 13: The Resampler's Spectral Response

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 channels, or as two segments of 32 complex words each to the zero padded data in order to suppress the interpolation support 2 resampler channels, or as a single segment of 64 images.
  • Page 127 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 The 12 bit filter coefficients are stored in a 256 word available to the resampler for each channel. The number of memory which can be divided into one, two, or four equal clock cycles available to the resampler is equal to the clock blocks.

  • Page 128: Overall Gain

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 PEAK COUNTER gain is: FINAL_SHIFT RES_SUM RES_GAIN ----------------------------------------------- × Each channel has a peak counter which can monitor the 32768 NDELAY input signal’s strength, or can count the number of overflows where RES_SUM is the sum of the QTAP coefficients.

  • Page 129: Output Modes

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 is set. The user can clear this bit by writing a 0 to the register. and 26, two for each of the four complex output words. Tags The control bit indicates that at least one sample overflowed are enabled using the TAG_EN control bit in address 17.

  • Page 130: Table 3: Output Mode Controls

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 Table 3: Output Mode Controls Suggested Default for Each Mode (hex values) Wide Word Serial modes Address Micro- Control Register micro- Parallel (Page 98) processor Nibble mode Link mode Four serial TDM output Asynchro- processor...

  • Page 131: Channel Output Map, Synchronous Four Channel Mode

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 Table 4: Channel Output Map, Synchronous Four Channel Mode CHANNEL OUTPUT PAGE 96 ADDRESSES OUTPUT_ORDER=0 OUTPUT_ORDER=1 OUTPUT_ORDER=2 16,17,18,19 , I-half , I-half , I-half 20,21,22,23 , Q-half , I-half , I-half 24,25,26,27 , I-half , Q-half...

  • Page 132: Figure 14: Wide Word Microprocessor Port

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 In the complex to real conversion modes (see Section channel is output. The REAL_ONLY mode is used with the 3.3.7), the real output is available in the Q portion of the complex to real conversion mode of the PFIR.
  • Page 133 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 samples) using the WORDS_PER_FRAME control in EN_RDY=1 in address 16) provides the frame strobe signal address 20. The WORDS_PER_FRAME control is usually and serial clock and a RDY start of frame pulse. The set to match the number of active output channels bidirectional RDY pin is an output pin from the master chip multiplexed onto each serial pin using the NSERIAL control.

  • Page 134: Figure 15: Serial Output Formats

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 clock is continuous The data pins go tristate after the last bit SOUT (a) SFS_MODE=3: FRAME SYNC AT THE START OF EACH WORD (16 bit words shown) SOUT (b) SFS_MODE=2: ONE FRAME SYNC AT THE START OF EACH COMPLEX WORD The minimum output frame length is set by FRAME_LENGTH SOUTA SOUTB...
  • Page 135 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 EN_RDY=1 in the master chip, and set MASTER=0 and by the I/Q pairs from channels B, C and D. If the channels are EN_RDY=0 in the slave chips. asynchronous, or initialization is not possible, then tag bits must be used to identify the channel data.

  • Page 136: Clocking

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 SFS (I Valid) RDY (Q Valid) P[0:23] (a) Synchronous Channels, SFS_MODE=0, BLOCK_SIZE=3 SFS (I or Q Valid) RDY (Frame Start) P[0:23] (b) Synchronous Channels, SFS_MODE=2, BLOCK_SIZE=3 SFS (I Valid) RDY (Q Valid) P[0:23] (c) Asynchronous Channels, SFS_MODE=0, BLOCK_SIZE=0 SFS (I or Q Valid)

  • Page 137: Power Down Modes

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 3.10 POWER DOWN MODES The 3 bit sync mode control for each sync circuit is defined in Table 7: The chip has a power down and clock loss detect circuit. Table 7: Sync Modes This circuit detects if the clock is absent long enough to cause dynamic storage nodes to lose state.

  • Page 138: Initialization

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 This arrangement allows the user to use the SO sync output (1) Reset the chip by setting address 0, the global reset register, to 0xF8; to synchronously drive the SIA or SIB sync inputs of all chips. sync source selected...

  • Page 139: Mask Revision Register

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 3.16 MASK REVISION REGISTER An 8 bit mask revision code (REVISION) can be read from address 27 of the output control page (page 98). The revision code allows users to determine, through software, what version of the GC4016 chips are being used. The current mask revision codes are: Table 9: Mask Revisions GC4016...

  • Page 140: Packaging

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 PACKAGING GC4016-PB 160 Ball Plastic Ball Grid Array (PBGA) The GC4016 chip is packaged in a 160 lead plastic ball grid array package. 1.56 mm 0.36 mm 13 mm 160 BALL PLASTIC BALL GRID ARRAY DIMENSION TOLERANCE 0.4 mm...

  • Page 141: Figure 18: Gc4016 Pin Assignments

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 Schematic symbols and pin assignments for the GC4016 in each of its input configurations are shown below. DIN13 (MSB) CIN13 (MSB) DIN12 (MSB) CIN13 (MSB) CIN12 CIN12 DIN12 CIN12 DIN11 CIN11 DIN10 CIN11 CIN10...

  • Page 142: Table 10: Gc4016 Pin Out Locations Top View

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 Table 10: GC4016 Pin Out Locations Top View VPAD VPAD VCORE VCORE VPAD VPAD VPAD AIN0 DIN13 DIN12 AIN2 AIN1 AIN3 DIN10 DIN11 DIN9 AIN5 AIN4 AIN6 DIN7 DIN8 DIN5 DIN6 TGND TGND VPAD...
  • Page 143 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 SIGNAL DESCRIPTION A,B,C, DIN INPUT DATA, Active high input pins The 14 bit 2’s complement input data for the four channels. The inputs are clocked into the chip on the rising edge of the clock (CK).

  • Page 144: Control Registers

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 CONTROL REGISTERS The chip is configured by writing to eight bit control registers. These registers are accessed for reading or writing using the control bus pins (CE, RD, WR, A[0:4], and C[0:7]) described in Section 3.1. The 32 word address space is split into eight global registers (addresses 0-7), eight unused registers (addresses 8-15) and 16 paged registers (addresses 16-31).
  • Page 145 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 ADDRESS 1: Status Register, Suggested default = 0x00 TYPE NAME DESCRIPTION 0 LSB READY The user sets this bit after reading the output registers. The chip clears this bit when new values have been loaded and it is time to read them. MISSED The chip sets this bit If the user has not set the READY bit before the chip loads the output registers.
  • Page 146 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 ADDRESS 4: General Sync Register, Suggested default = 0x27, Cleared by power up TYPE NAME DESCRIPTION DIAG_SYNC The Checksum generator is strobed by this sync. See Table 7 for the possible (LSB) sync selections.

  • Page 147: Paged Registers

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 PAGED REGISTERS Addresses 16 to 31 are used in pages as determined by the page map register (address 2). Table 12: Page Assignments Page Description Channel A CFIR Coefficients Channel A PFIR Coefficients Channel A Frequency Channel A Control Channel B CFIR Coefficients...

  • Page 148: Cfir Coefficient Pages

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 CFIR COEFFICIENT PAGES The user programmable filter CFIR coefficients are stored using pages 0 and 1 for channel A, pages 8 and 9 for channel B, pages 16 and 17 for channel C, and pages 24 and 25 for channel D. Table 13: CFIR Coefficient Pages Pages 0, 8, 16, or 24 Pages 1, 9, 17, or 25...

  • Page 149: Channel Frequency Pages

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 Coefficient h is the first coefficient and coefficient h is the center coefficient of the filter’s impulse response. The 16 bit 2’s complement coefficients are stored in two bytes, least significant byte first, for example, the LSBs of coefficient 0 are stored in address 16 and the MSBs in address 17.

  • Page 150: Channel Control Pages

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 CHANNEL CONTROL PAGES These pages contain the various control settings for the four channels. To configure channels A, B, C and D use pages 7, 15, 23, and 31 respectfully. All registers are read/write. The following table summarizes the registers: Table 15: Channel Control Registers ADDRESS NAME...
  • Page 151 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 ADDRESS 18: NCO Sync, Suggested default = 0x22 TYPE NAME DESCRIPTION 0-2 LSB NCO_SYNC The NCO is initialized to the phase setting by this sync Unused DITHER_SYNC The dither circuit is reset by this sync to zero. 7 MSB Unused These syncs use the selections shown in Table 7.
  • Page 152 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 ADDRESS 21: Decimation Ratio Byte 0, Suggested default = 0x07 TYPE NAME DESCRIPTION DEC[0:7] The LSBs of the decimation control ADDRESS 22: Decimation Ratio Byte 1, Suggested default = 0x70 TYPE NAME DESCRIPTION DEC[8:11]...
  • Page 153 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 ADDRESS 25: CFIR, Suggested default = 0x00 TYPE NAME DESCRIPTION 0 LSB NO_SYM_CFIR When this bit is high, CFIR is an 11 tap asymmetric filter. Coefficient h multiplied by the newest data. QDLY_CFIR Delay the Q sample stream by one CFIR input sample.
  • Page 154 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 ADDRESS 28: Peak Control, Suggested default = 0x1D TYPE NAME DESCRIPTION 0-2 LSB PEAK_SYNC Synchronizes the peak counter circuitry using the mode selected in Table 7. When the selected sync occurs, the counter transfers its contains to a read only control register and clears the counter.

  • Page 155: Resampler Coefficient

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 RESAMPLER COEFFICIENT PAGES (PAGES 32-63) These pages store the 256 resampler coefficients. Storing resampler coefficient values is similar to storing the coefficients for the CFIR and PFIR filters. The resampler coefficients are 12 bits with the 8 LSBs written in one address, and the upper 4 bits written as the 4 LSBs of the next address.

  • Page 156: Resampler Control Page

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 RESAMPLER CONTROL PAGE (PAGE 64) This page controls the resampler. The address assignments are: Table 17: Resampler Control Registers ADDRESS NAME DESCRIPTION N-channels Sets the number of channels and filters N-Multiplies Sets the number of multiplies per output Filter Select Maps channels to filter sets...
  • Page 157 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 ADDRESS 19: Final Shift Register, Suggested default = 0x34 TYPE NAME DESCRIPTION 0-3 LSB FINAL_SHIFT The final shift up applied to all output channels before rounding and outputting. Legal values are 0-15. ROUND Round the output to 12 (ROUND=0), 16 (ROUND=1), 20 bits (ROUND=2) or 24 bits (ROUND=3).

  • Page 158: Resampler Ratio Page

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 dividing the clock so far that there is not enough clock cycles to complete the computations (see Section 3.5). It is recommended that an application first be brought up without resampler clock division. ADDRESS 23: Ratio Map Register Suggested default = 0x00 TYPE...

  • Page 159: Output Control Page

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 5.11 OUTPUT CONTROL PAGE (PAGE 98) This page controls the output. The following table summarizes the registers: Table 19: Output Control Registers ADDRESS NAME DESCRIPTION Tristate Controls Enables serial and parallel ports and controls. Output Format Sync output.
  • Page 160 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 ADDRESS 17: Output Format, Suggested default = 0x40 TYPE NAME DESCRIPTION 0 (LSB) INV_SCK Invert SCK output. The serial, nibble, link and parallel outputs normally change on the rising edge of SCK. If INV_SCK is set high the clock is inverted so data changes on the falling edge.
  • Page 161 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 ADDRESS 19: Output Frame Control, Suggested default = (see Table 3) TYPE NAME DESCRIPTION 0-5 (LSB) FRAME_LENGTH Used in the serial and nibble modes to set the frame length, and is not used in the microprocessor, link or parallel modes.
  • Page 162 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 ADDRESS 20: Output Word Sizes, Suggested default = (see Table 3) TYPE NAME DESCRIPTION 0-2 (LSB) WORDS_PER_FRAME Serial, nibble and parallel modes: The number of output words (not complex pairs) in a frame is (WORDS_PER_FRAME+1).
  • Page 163 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 ADDRESS 21: Output Clock Control, Suggested default = (see Table 3) TYPE NAME DESCRIPTION 0-3 (LSB) SCK_RATE Serial clock rate is SCK = CK/(1+SCK_RATE). SCK_RATE can be 0 to 15. If SCK_RATE=0, then the serial clock rate will be equal to CK.
  • Page 164 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 ADDRESS 23: Output Tag A, Suggested default = 0x10 TYPE NAME DESCRIPTION 0-3 (LSB) TAG_AI Four bit tag for serial stream A, I word. 4-7 (MSB) TAG_AQ Four bit tag for serial stream A, Q word. ADDRESS 24: Output Tag B, Suggested default = 0x32 TYPE...
  • Page 165 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 THIS PAGE IS INTENTIONALLY BLANK © GRAYCHIP,INC. - 52 - August 27, 2001 This document contains information which may be changed at any time without notice...

  • Page 166: Specifications

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Table 20: Absolute Maximum Ratings CAUTION: Exceeding the absolute maximum ratings (min or max) may cause permanent damage to the part. These are stress only ratings and are not intended for operation. PARAMETER SYMBOL UNITS...

  • Page 167: Power Consumption

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 POWER CONSUMPTION The maximum power consumption is a function of the operating mode of the chip. The following equation estimates the typical power supply current for the chip. Chip to chip variation is typically +/- 5%. Table 24 provides maximum current in a maximum configuration used in production test.

  • Page 168: Ac Characteristics

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 AC CHARACTERISTICS Table 24: AC Characteristics (-40 TO +85 C Case, across recommended voltage range, unless noted) TEST PARAMETER SYMBOL UNITS LEVEL Clock Frequency Note 1 Clock low or high period CKL/H Clock Duty Cycle (t as a percentage of the clock period)

  • Page 169: Application Notes

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 APPLICATION NOTES POWER AND GROUND CONNECTIONS The GC4016 chips are very high performance chips which require solid power and ground connections to avoid noise on the V and GND pins. If possible the GC4016 chip should be mounted on a circuit board with dedicated power and CORE ground planes and with at least two decoupling capacitors (0.01µf) adjacent to each side of the chip, one for V and one for...

  • Page 170: Example Cfir Filter Sets

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 EXAMPLE CFIR FILTER SETS The CFIR filter must be flat over the output passband of interest, and have a stopband which rejects out of band signals which will fall into the passband of interest. The spectral requirements of this filter are shown in Figure 10 in Section 3.3.5. The CFIR filter must also compensate for the passband roll off of the CIC filter.

  • Page 171: Example Pfir Filter Sets

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 EXAMPLE PFIR FILTER SETS The spectral requirements of the PFIR filter are shown in Figure 11 in Section 3.3.6. The filters in Table 26 provide passband bandwidths which are between 17% and 150% of the down converter channel output sample rate (before resampling). The filter taps can be copied from this table, or requested by e-mail from tech-support@graychip.com, or downloaded from the web at www.graychip.com.

  • Page 172: Figure 19: Overall Spectral Responses Of Example Filters

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 cfir_17 with pfir_17 cfir_34 with pfir_34 cfir_68 with pfir_68 cfir_80 with pfir_80 cfir_100 with pfir_100 cfir_150 with pfir_150 Figure 19. Overall Spectral Responses of Example Filters © GRAYCHIP,INC. - 59 - August 27, 2001 This document contains information which may be changed at any time without notice...

  • Page 173: Example Resampler Configurations

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 EXAMPLE RESAMPLER CONFIGURATIONS This Section describes some commonly used resampler configurations and the filter coefficient sets used for them. 7.7.1 Bypass Mode The resampler is bypassed by using a configuration which has h set to 1024, all other taps set to zero, NMULT set to 7, NO_SYM_RES set to 1, FINAL_SHIFT set to 5, and RATIO set to 2 (0x04000000).

  • Page 174: Gc4016 Configuration Generator

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 GC4016 CONFIGURATION GENERATOR A GC4016 configuration generator is available from Graychip in the form of a “C” program which can be obtained via email or the web. The program is described below. Usage: cmd4016 [-gc100 | -TI | -sim] <config_file>...

  • Page 175: Example Gsm Application

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 EXAMPLE GSM APPLICATION This section describes how to configure the chip to downconvert GSM (or EDGE) signals and meet the stringent GSM processing specifications. The desired GSM Specifications are: Table 29: Desired GSM Specifications Specification Value Comment...

  • Page 176: Table 30: Example Gsm Configuration

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 7.9.2 Oversampling Using the Resampler This example assumes the input sample rate is equal to 4*N*B, where N is the decimation in the CIC filter (See Section 5.6) and B is the GSM bit rate (270.833 KHz). The outputs are one complex sample per bit (270.833 KHz) with the resampler set to interpolate by unity (no interpolation).

  • Page 177: Example Is-136 Damps Application

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 7.10 EXAMPLE IS-136 DAMPS APPLICATION This section describes how to configure the chip to downconvert DAMPS signals, apply the root-raised-cosine receive filter, and output samples at two times, four times or eight times the DAMPS symbol rate. The desired DAMPS Specifications are: Table 31: Desired DAMPS Specifications Specification Value...

  • Page 178: Table 32: Example Damps Configuration

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 ratio. The resampler uses the configuration res_15x32_80. (See Section 7.7). This configuration introduces 0.05dB of passband ripple and -58dB inband noise, neither being large enough to effect the BER. The resampler ratio for two samples per symbol (48.6KHz) is 0x04000000, for four samples per symbol (97.2KHz) is 0x02000000, and for eight samples per symbol (194.4KHz) is 0x01000000.

  • Page 179: Nb-Cdma Application

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 7.11 EXAMPLE IS-95 NB-CDMA APPLICATION This section describes how to configure the chip to downconvert IS-95 NB-CDMA signals and output samples at two times (2X), four times (4X) or eight times (8X) the IS-95 symbol rate of 1.2288MHz. The desired IS-95 Specifications are: Table 33: Desired IS-95 NB-CDMA Specifications Specification Value...
  • Page 180 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 7.11.2 Oversampling Using the Resampler This example assumes the input sample rate is equal to 6*N*B, where N is the decimation in the CIC filter (See Section 5.6) and B is the IS95 symbol rate (1.2288 MHz). The PFIR filter output rate is 1.5 samples per symbol (1.5X). The outputs are two complex samples per symbol (2.4576 MHz) if the resampler is set to interpolate by 4/3.

  • Page 181: Umts Wb-Cdma Application

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 7.11.4 IS95 NB-CDMA Configuration The control register settings for this example are shown in table 34. It is assumed that output pin SO is tied to input pin SIA. Table 34: Example IS95 NB-CDMA Configuration Global Registers Address After configuration set address 0 to 08, then set address 5 to 5C...

  • Page 182: Figure 23: Frequency Response For The Example Umts Application

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 7.12.1 UMTS Filter Response Figure 23 shows the overall response using specially tuned CFIR and PFIR filters., The PFIR filter is a specially optimized root-raised-cosine 63 tap filter with an alpha of 0.22. The filter is designed to have less than -50dB of inter symbol interference (ISI) noise.

  • Page 183: Example Umts Configuration

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 RES_SUM=134782 and NDELAY=64. Because of the loss of 1/2 when converting real data to complex, the desired gain is 2.0. This can be achieved by setting FINE_GAIN to 2352 and FINAL_SHIFT equal to 4. 7.12.4 UMTS Configuration The control register settings for this example are shown in table 36.

  • Page 184: Diagnostic Test 1

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 7.13 DIAGNOSTICS The following four tables contain the diagnostic test configurations. To run the diagnostics, load the GC4016 with the configuration, set address 0 to 00 in order to clear the resets, set address 5 to 00 to release the counter, wait for the checksum to stabilize (approximately 2 clock cycles) and then read the checksum, which should match the expected value.

  • Page 185: Diagnostic Test 3

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 Table 39: Diagnostic Test 3, Expected Checksum = EF PAGED REGISTERS PAGE ADDRESS CFIR COEFFICIENT PAGES: 0,1,8,9,16,17,24,25 0,8,16,24 1,9,17,25 PFIR COEFFICIENT PAGES: 2,3,4,5,10,11,12,13,18,19,20,21,26,27,28,29 FREQUENCY TUNING PAGES: GENERAL CONTROL PAGES: 7,15,23,31 RESAMPLER COEFFICIENT PAGES: RESAMPLER CONTROL PAGE: RESAMPLER RATIO PAGE: OUTPUT PAGE:...

  • Page 186: Diagnostic Test 4

    GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 Table 40: Diagnostic Test 4, Expected Checksum = 18 PAGED REGISTERS PAGE ADDRESS CFIR COEFFICIENT PAGES: 0,1,8,9,16,17,24,25 0,8,16,24 1,9,17,25 PFIR COEFFICIENT PAGES: 2,3,4,5,10,11,12,13,18,19,20,21,26,27,28,29 FREQUENCY TUNING PAGES: GENERAL CONTROL PAGES: 7,15,23,31 7,23 15,31 RESAMPLER COEFFICIENT PAGES: 33-63...
  • Page 187 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 Graychip reserves the right to make changes in circuit design and/or specifications at any time without notice. The user is cautioned to verify that datasheets are current before placing orders. Information provided by Graychip is believed to be accurate and reliable.

  • Page 188: Sync Modes

    GC4016 REGISTER ASSIGNMENT QUICK REFERENCE GUIDE Suggested Page Address Name 7(MSB) 0(LSB) Default Global Global Reset GLOBAL_ OUT_BLK_ PAD_RESET RESAMPLER_ EDGE_WRITE CK_2X_EN CK_2X_TEST CK_LOSS_ F8 then 08 RESET RESET RESET DETECT See below Status ZERO CHECK_DONE RES_QOV RES_IOV MISSED READY Page PAGE[0:6] Checksum...
  • Page 189 GC4016 REGISTER ASSIGNMENT QUICK REFERENCE GUIDE Suggested Page Address Name 7(MSB) 0(LSB) Default 32-63 16-31 Filter Taps Resampler Coefficients, 8 LSBs in even addresses, 4 MSBs in odd addresses. (Must be loaded in the blocks 16-23 and 24-31) Bypass 16 (0x10) N-Channels RES_SYNC NF=(NFILTER-1)
  • Page 190 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

  • Page 191: D.1 Introduction

    P e nte k M o d e l 6 2 3 0 / 6 23 1 O p e r a t in g M a nu a l Pa ge D− 1 Appendix D: Analog Devices ADM1024 System Hardware Monitor Introduction The following pages are a reprint of the Analog Devices ADM1024 System Hardware...
  • Page 192 Page D−2 Pentek Mo d el 6230/6231 Oper a ting Ma nu al Thi s p age is i nten tio na lly b lan k Rev.: B.4...
  • Page 193 System Hardware Monitor with Remote Diode Thermal Sensing ADM1024 FEATURES APPLICATIONS Up to Nine Measurement Channels Network Servers and Personal Computers Inputs Programmable-to-Measure Analog Voltage, Fan Microprocessor-Based Office Equipment Speed or External Temperature Test Equipment and Measuring Instruments External Temperature Measurement with Remote Diode (Two Channels) PRODUCT DESCRIPTION The ADM1024 is a complete system hardware monitor for...
  • Page 194 1, 2 ADM1024–SPECIFICATIONS to T to V , unless otherwise noted) Parameter Unit Test Conditions/Comments POWER SUPPLY Supply Voltage, V 3.30 Supply Current, I Interface Inactive, ADC Active ADC Inactive, DAC Active µA Shutdown Mode TEMPERATURE-TO-DIGITAL CONVERTER ± 3 °C 0°C ≤...
  • Page 195 ADM1024 Parameter Unit Test Conditions/Comments SERIAL BUS DIGITAL INPUTS (SCL, SDA) Input High Voltage, V Input Low Voltage, V Hysteresis Glitch Immunity DIGITAL INPUT LOGIC LEVELS (See Note 7) (ADD, CI, RESET, VID0–VID4, FAN1, FAN2) Input High Voltage, V = 2.85 V – 5.5 V Input Low Voltage, V = 2.85 V –...

  • Page 196: Absolute Maximum Ratings

    ADM1024 PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS* Positive Supply Voltage (V ) ..... 6.5 V Voltage on 12 V V Pin ......20 V NTEST OUT/ADD VID0/IRQ0 Voltage on AOUT, N TEST_OUT ADD, 2.5 V...
  • Page 197 ADM1024 PIN FUNCTION DESCRIPTIONS Mnemonic Description NTEST_OUT/ADD Digital I/O. Dual Function pin. This is a three-state input that controls the 2 LSBs of the Serial Bus Address. This pin functions as an output when doing a NAND test. THERM Digital I/O. Dual Function pin. This pin functions as an interrupt output for temperature interrupts only, or as an interrupt input for fan control.
  • Page 198 ADM1024–Typical Performance Characteristics DXP TO GND –10 DXP TO V (5V) –20 –30 –40 –50 –60 MEASURED TEMPERATURE LEAKAGE RESISTANCE – M ® TPC 1. Temperature Error vs. PC Board Track Resistance TPC 4. Pentium III Temperature Measurement vs. ADM1024 Reading 250mV p-p REMOTE 100mV p-p REMOTE –5...
  • Page 199 ADM1024 Pins 15, 16, and 19 are dedicated analog inputs with on-chip 26.5 attenuators, configured to monitor 12 V, 5 V and the processor 26.0 core voltage, respectively. Pins 17 and 18 may be configured as analog inputs with on-chip 25.5 = 3.3V attenuators to monitor a second processor core voltage and a...
  • Page 200 ADM1024 Configuration Registers: Provide control and configuration. condition, and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/W bit, which determines Channel Mode Register: Stores the data for the operating the direction of the data transfer, i.e., whether data will be modes of the input channels.
  • Page 201 ADM1024 ACK. BY START BY ACK. BY ADM1024 MASTER ADM1024 FRAME 1 FRAME 2 SERIAL BUS ADDRESS BYTE ADDRESS POINTER REGISTER BYTE SCL (CONTINUED) SDA (CONTINUED) ACK. BY STOP BY ADM1024 MASTER FRAME 3 DATA BYTE Figure 2a. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register ACK.
  • Page 202 ADM1024 Table II. Channel Mode Register Channel Mode Register Bit Controls Pin(s) Function 0 = FAN1, 1 = AIN1 0 = FAN2, 1 = AIN2 17, 18 0 = 2.5 V, V , 1 = D2–, D2+ CCP2 Int. V Meas.
  • Page 203 ADM1024 A-TO-D CONVERTER – . ) These inputs are multiplexed into the on-chip, successive approximation, analog-to-digital converter. This has a resolution of eight bits. The basic input range is zero to 2.5 V, which is Negative and bipolar input ranges can be accommodated by the input range of AIN1 and AIN2, but five of the inputs have using a positive reference voltage to offset the input voltage range built-in attenuators to allow measurement of 2.5 V, 5 V, 12 V...
  • Page 204 ADM1024 Register (address 4Bh). As both positive and negative tempera- To prevent ground noise from interfering with the measurement, tures can be measured, the temperature data is stored in two’s the more negative terminal of the sensor is not referenced to complement format, as shown in Table IV.
  • Page 205 ADM1024 As the ADC will normally be left to free-run in this manner, the 10MIL time taken to monitor all the analog inputs will normally not be 10MIL of interest, as the most recently measured value of any input can be read out at any time.
  • Page 206 ADM1024 Suitable fan drive circuits are given in Figures 9a to 9f. When 4. The op amp may be powered from the 12 V rail alone or from ±12 V. If it is powered from 12 V then the input common- using any of these circuits, the following points should be noted: mode range should include ground to accommodate the 1.
  • Page 207 ADM1024 6. In all these circuits, the output transistor must have an I LAYOUT AND GROUNDING CMAX Analog inputs will provide best accuracy when referred to a clean greater than the maximum fan current, and be capable of dissipating power due to the voltage dropped across it when ground.
  • Page 208 ADM1024 If the fan has a strong pull-up (less than 1 kΩ) to 12 V, or a The monitoring cycle begins when a one is written to the Start Bit (Bit 0), and a zero to the INT_Clear Bit (Bit 3) of the totem-pole output, then a series resistor can be added to limit the Configuration Register.
  • Page 209 ADM1024 measurement. Therefore, if the start of a fan measurement just The chassis intrusion circuit should be designed so that it can be misses a rising edge, the measurement can take almost three tach reset by pulling its output low. A suitable chassis intrusion circuit periods.
  • Page 210 ADM1024 to be asserted. After masking, the status bits are all OR’d or clearing Bits 4 to 6 of the Channel Mode Register and Bits together to produce the INT output, which will pull low if any 6 and 7 of Configuration Register 2 (address 4Ah). These interrupt unmasked status bit goes high, i.e., when any measured value inputs are not latched in the ADM1024, so they do not require goes out of limit.
  • Page 211 ADM1024 a. the temperature rises above the high limit INTERRUPT STATUS MIRROR REGISTERS Whenever a bit in one of the Interrupt Status Registers is updated, the same bit is written to duplicate registers at addresses 4Ch b. the low limit is/are reprogrammed, and the temperature then and 42h.
  • Page 212 ADM1024 If THERM is cleared by reading the status register, it will be In NAND test mode, all digital inputs may be tested as illustrated reasserted after the next temperature reading and comparison if below. NTEST_OUT/ADD will become the NAND test output it remains above the high limit.
  • Page 213 ADM1024 USING THE CONFIGURATION REGISTERS STARTING CONVERSION Control of the ADM1024 is provided through two configuration The monitoring function (analog inputs, temperature, and fan registers. The ADC is stopped upon power-up, and the INT_Clear speeds) in the ADM1024 is started by writing to Configuration signal is asserted, clearing the INT output.
  • Page 214 ADM1024 THERM I/O TO OTHER CIRCUITS VID0/IRQ0 NTEST OUT/ADD THERM VID1/IRQ1 FROM VID PINS VID2/IRQ2 SERIAL BUS PROCESSOR 1N914 1N914 VID3/IRQ3 MRD901 FAN1/AIN1 CMOS VID4/IRQ4 74HC132 BACKUP ADM1024 BATTERY FAN2/AIN2 100k CCP1 +2.5V /D2+ 470k GND D /D2– CCP2 10 F 0.1 F INT TO PROCESSOR +12V...
  • Page 215 ADM1024 ADM REGISTERS Table VI. Address Pointer Register Name Description 7–0 Address Pointer Write Address of ADM1024 Registers. See the tables below for detail. Table VII. List of Registers Power-On Value Address Description (Binary Bit 7–0) Notes Internal Temperature = 70°C Can be written only if the write once bit in Configuration Hardware Trip Point Register 2 has not been set.
  • Page 216 ADM1024 Table VII (continued) Power-On Value Address Description (Binary Bit 7–0) Notes High Limit Indeterminate CCP2 Low Limit Indeterminate CCP2 Ext Temp1. High Limit Indeterminate Stores high limit for a diode sensor connected to Pins 13 and 14. Ext Temp1. Low Limit Indeterminate Stores low limit for a diode sensor connected to Pins 13 and 14.
  • Page 217 ADM1024 Table IX. Register 40h, Configuration Register 1 (Power-On Default = 08h) Bit Name Description START Logic 1 enables start-up of ADM1024, logic 0 places it in standby mode. Caution: The outputs of the interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred (see “INT Clear”...
  • Page 218 ADM1024 Table XII. Register 43h, INT Interrupt Mask Register 1 (Power-On Default = 00h) Bit Name Description A one disables the corresponding interrupt status bit for INT interrupt. 2.5 V/Ext. Temp2 Read/Write A one disables the corresponding interrupt status bit for INT interrupt. Read/Write CCP1 A one disables the corresponding interrupt status bit for INT interrupt.
  • Page 219 ADM1024 Table XVII. Register 4AH, Configuration Register 2 (Power-On Default [7:0] = 0x00h) Name Description Thermal INT Setting this bit masks the thermal interrupts for the INT output ONLY. The Read/Write THERM output will still be generated, regardless of the setting of this bit. Mask Ambient Temp Read/Write...
  • Page 220 ADM1024 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead TSSOP Package (RU-24) 0.311 (7.90) 0.303 (7.70) 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) PIN 1 0.006 (0.15) 0.0433 (1.10) 0.002 (0.05) 0.0256 (0.65) 0.0118 (0.30) 0.028 (0.70) SEATING 0.0079 (0.20) 0.0075 (0.19) 0.020 (0.50)

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