Pentek 6230 Operating Manual page 216

ADM1024
Hex
Address Description
35h V High Limit
CCP2
36h V Low Limit
CCP2
37h Ext Temp1. High Limit
38h Ext Temp1. Low Limit
39h Internal Temp. High Limit
3Ah Internal Temp. Low Limit
3Bh AIN1/FAN1 High Limit
3Ch AIN2/FAN2 High Limit
3Dh Reserved
3Eh Company ID Number
3Fh Revision Number
40h Configuration Register 1
41h Interrupt INT Status Register 1
42h Interrupt INT Status Register 2
43h INT Mask Register 1
44h INT Mask Register 2
46h Chassis Intrusion Clear Register
47h VID 0–3/Fan Divisor Register
49h VID4 Register
4Ah Configuration Register 2
4Ch Interrupt Status Register
Mirror No. 1
4Dh Interrupt Status Register
Mirror No. 2
Table VIII. Register 16h, Channel Mode Register (Power-On Default = 00h)
Bit Name R/W
0 FAN1/AIN1 R/W
1 FAN2/AIN2 R/W
2 2.5 V, V /D2 R/W
CCP
3 Int V R/W
CC
4 IRQ0 EN R/W
5 IRQ1 EN R/W
6 IRQ2 EN R/W
7 VID/IRQ R/W
Table VII (continued)
Power-On Value
(Binary Bit 7–0)
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
0100 0001
0001 nnnn
0000 1000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0101 (VID3–VID0) See Table XV.
1000 000 (VID4)
0000 0000
0000 0000
0000 0000
Description
Clearing this bit to 0 configures Pin 5 as FAN1 input. Setting this bit to 1 configures Pin 5 as AIN1.
Power-on default = 0.
Clearing this bit to 0 configures Pin 6 as FAN2 input. Setting this bit to 1 configures Pin 6 as AIN2.
Power-on default = 0.
Clearing this bit to 0 configures Pins 17 and 18 to measure 2.5 V and V
configures Pins 18 and 19 as an input for a second remote temperature-sensing diode. Power-on
default = 0.
Clearing this bit to 0 sets the measurement range for the internal V
this bit to 1 sets the internal V
Setting this bit to 1 enables Pin 24 as an active high interrupt input, provided Pins 20 to 24 have
been configured as interrupts by setting Bit 7 of the Channel Mode Register. Power-on default = 0.
Setting this bit to 1 enables Pin 23 as an active high interrupt input, provided have been configured
as interrupts by setting Bit 7 of the Channel Mode Register. Power-on default = 0.
Setting this bit to 1 enables Pin 22 as an active high interrupt input, provided Pins 20 to 24 have
been configured as interrupts by setting Bit 7 of the Channel Mode Register. Power-on default = 0.
Clearing this bit to 0 configures Pins 20 to 24 as processor voltage ID inputs. Setting this bit to 1
configures Pins 20 to 24 as interrupt inputs. Power-on default = 0.
Notes
Stores high limit for a diode sensor connected to Pins 13
and 14.
Stores low limit for a diode sensor connected to Pins 13
and 14.
Stores the high limit for the internal temperature reading.
Stores the low limit for the internal temperature reading.
Stores high limit for AIN1 or FAN1, depending on the
configuration of Pin 5.
Stores high limit for AIN2 or FAN2, depending on the
configuration of Pin 6.
This location will contain the company identification number
(Read Only).
Last four bits of this location will contain the revision number
of the part. (Read Only)
See Table IX.
See Table X.
See Table XI.
See Table XII.
See Table XIII.
See Table XIV.
See Table XVI.
See Table XVII.
See Table XVIII.
See Table XIX.
measurement range to 5 V. Power-on default = 0.
CC
–24–
. Setting this bit to 1
CCP2
measurement to 3.3 V. Setting
CC
REV. A