Pentek 6231 Manuals

Manuals and User Guides for Pentek 6231. We have 1 Pentek 6231 manual available for free PDF download: Operating Manual

Pentek 6231 Operating Manual

Pentek 6231 Operating Manual (220 pages)

32/16?Channel Digital Receiver VIM Module for Pentek VIM Baseboards

Brand: Pentek | Category: Receiver | Size: 3.24 MB

Table of Contents

Table of Contents

3
- Model
  2
- Chapter 1: Introduction
  
  9
  - Features
    9
  - General Description
    9
  - Analog/Digital Conversion
    10
  - Digital Interfaces
    10
  - Digital Receivers
    10
  - Interrupts
    11
  - Timing and Synchronization
    11
  - VIM Interface
    11
  - Block Diagrams
    12
    
    Figure 1−3: Model 6230 Block Diagram, with Option 105
    13
    
    Channels
    14
  - FPGA Configuration
    15
    
    Model 6230
    16
    
    Model 6231
    17
  - Board Support Software
    17
  - Specifications
    18
- Chapter 2: Installation and Connections
  
  21
- Chapter 3: Memory Maps and Register Descriptions
  
  41
  - Model 6230/6231 Memory Map
    41
  - Overview
    41
  - Table 3−3: Model 6230/6231 Memory Map
    42
  - Virtex Config Register
    43
    
    Busy
    43
    
    Init
    43
    
    Write
    43
    
    Done
    44
    
    Ld Src
    44
    
    Prgm
    44
  - Virtex Config Data Register
    44
  - Wait States Register
    45
  - Hardware Monitor Port Register
    46
  - Table 3−8: ADM1024 Registers
    47
  - Master Control Register
    48
    
    Reset
    48
    
    Sync Src
    48
    
    Clk Src Sel
    49
    
    Ext Sync en
    49
    
    MCLK Divn
    49
    
    Osc Dsbl
    49
    
    Sync Pol
    49
    
    Ext Clk
    50
    
    Mastr
    50
    
    Term
    50
  - Bypass Rate Divide Register
    51
  - Channel Enable Register
    52
  - Gate Control Register
    53
    
    INT EDGE X
    53
    
    Gate Disbl
    54
    
    Gate Pol
    54
    
    GATE Seln
    54
    
    Gate Src
    54
    
    Trig Clear
    54
    
    Ext Gate
    55
    
    Gate/Trig
    55
    
    Hold Mode
    55
  - Trigger Length Register
    56
  - Channel Control Register
    57
    
    DIV Rst en
    57
    
    Fmtr en
    57
    
    Reset
    57
    
    DAT Moden
    58
  - Sync/Gate Generator Register
    59
    
    Fifo Gate
    59
    
    Sync
    59
  - Interrupt Mask Register
    60
  - Table 3−18: Interrupt Register Bits
    61
  - Interrupt Flag Register
    62
  - Interrupt Status Register
    63
  - Semaphore Register
    64
  - I/O Direction 2 Register (Model 6231 Only)
    65
  - I/O Data 2 Register (Model 6231 Only)
    66
  - I/O Direction Register
    67
  - I/O Enable Register
    68
    
    I/O En1
    68
    
    I/O En2
    68
  - I/O Data Register
    69
  - Graychip 0 & 1 Registers
    70
- Chapter 4: Data Formatting and Routing
  
  71
  - Data Routing and Formats
    71
    
    DDR Bypass Mode, A/D Data, Time Packed (010)
    72
    
    DDR Bypass Mode, A/D Data, Unpacked (001)
    72
    
    DDR Bypass Mode, A/D Data, Channel Packed (011)
    73
    
    DDR Mode, 16−Bit, Unpacked I/Q, Tagged (100)
    74
    
    DDR Mode, 24−Bit, Unpacked I/Q, Tagged (101)
    75
    
    DDR Mode, 16−Bit, Packed I/Q (110)
    76
    
    DDR Mode, 24−Bit, Packed I/Q (111)
    77
- Chapter 5: Timing and Synchronization
  
  79
  - Overview
    71
  - Overview
    79
  - Clock
    80
  - Figure 5−2: Model 6231 Gate/Sync/Clock Logic
    80
  - Sync
    80
  - Gates
    81
    
    A.1 Introduction
    83
    
    Table A−2: EEPROM Example (Model 6230 Shown)
    84
    
    B.1 Introduction
    85
    
    C.1 Introduction
    107
Table of Contents

112
- Block Diagram
  114
- Figure 1: GC4016 Block Diagram
  114
- Key Features
  114
- Functional Description
  115
  - Control Interface
    115
  - Figure 2: Normal Control I/O Timing
    116
  - Figure 3: Edge Write Control Timing
    116
  - Input Format
    117
  - The down Converters
    117
  - Table 1: Input Mode Controls
    117
  - Figure 4: the down Converter Channel
    118
  - Figure 5: Zero Pad Synchronization
    119
  - Figure 6: NCO Circuit
    119
  - Figure 7: Example NCO Spurs
    120
  - Figure 8: NCO Peak Spur Plot
    120
  - Figure 9: Five Stage CIC Decimate by N Filter
    121
  - Figure 10: Typical CFIR Specifications
    122
  - Figure 11: Typical PFIR Specifications
    122
  - Multichannel Modes
    123
  - Resampler
    125
  - Figure 12: Resampler Channel Block Diagram
    125
- Multichannel Mode Settings
  125
- Figure 13: the Resampler's Spectral Response
  126
  - Overall Gain
    128
  - Peak Counter
    128
  - Output Modes
    129
  - Table 3: Output Mode Controls
    130
- Channel Output Map, Single Channel Mode
  131
- Channel Output Map, Synchronous Four Channel Mode
  131
- Channel Output Map, Synchronous Two Channel Mode
  131
- Figure 14: Wide Word Microprocessor Port
  132
- Figure 15: Serial Output Formats
  134
  - Clocking
    136
  - Figure 16: Parallel Mode Timing
    136
  - Power down Modes
    137
  - Synchronization
    137
  - Table 8: Recommended Sync Settings
    137
  - Initialization
    138
  - Data Latency
    138
  - Diagnostics
    138
  - Jtag
    138
  - Mask Revision Register
    139
- Mask Revisions
  139
- Packaging
  140
- Control Registers
  144
  - Global Controls
    144
  - Table 11: Global Control Registers
    144
  - Paged Registers
    147
  - Cfir Coefficient Pages
    148
  - Pfir Coefficient Pages
    148
  - Channel Frequency Pages
    149
  - Channel Control Pages
    150
- Channel Control Registers
  150
  - Resampler Coefficient
    155
- Resampler Coefficient Pages (Single Filter Mode)
  155
  - Resampler Control Page
    156
- Resampler Control Registers
  156
  - Resampler Ratio Page
    158
  - Channel Output
    158
  - Output Control Page
    159
  - Table 19: Output Control Registers
    159
- Specifications
  166
  - Absolute Maximum Ratings
    166
  - Recommended Operating Conditions
    166
  - Thermal Characteristics
    166
- Thermal Data
  166
  - Power Consumption
    167
  - DC Characteristics
    167
  - Table 23: DC Operating Conditions
    167
  - Ac Characteristics
    168
- Application Notes
  169
  - Power and Ground Connections
    169
  - Static Sensitive Device
    169
  - Moisture Sensitive Package
    169
  - Thermal Management
    169
  - Example Cfir Filter Sets
    170
- Example CFIR Filters
  170
- Example IS95 NB-CDMA Configuration
  181
- Table 35: Desired UMTS Specifications
  181
- Figure 23: Frequency Response for the Example UMTS Application
  182
- Example UMTS Configuration
  183
- Graychip,Inc
  183
- Diagnostic Test 1
  184
- Diagnostic Test 2
  184
- Diagnostic Test 3
  185
- Diagnostic Test 4
  186
  - Output Test Configuration
    186
- CFIR Coefficient
  188
- PFIR Coefficient
  188
  - D.1 Introduction
    191
- Sync Modes
  188
- Absolute Maximum Ratings
  196

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