Pentek 6230 Operating Manual page 195

Parameter
SERIAL BUS DIGITAL INPUTS
(SCL, SDA)
Input High Voltage, V
IH
Input Low Voltage, V
IL
Hysteresis
Glitch Immunity
DIGITAL INPUT LOGIC LEVELS
(ADD, CI, RESET, VID0–VID4, FAN1, FAN2)
Input High Voltage, V
IH
Input Low Voltage, V
IL
NTEST_IN
Input High Voltage, V
IH
DIGITAL INPUT CURRENT
Input High Current, I
IH
Input Low Current, I
IL
Input Capacitance, C
IN
8
SERIAL BUS TIMING
Clock Frequency, f
SCLK
Glitch Immunity, t
SW
Bus Free Time, t
BUF
Start Setup Time, t
SU;STA
Start Hold Time, t
HD;STA
SCL Low Time, t
LOW
SCL High Time, t
HIGH
SCL, SDA Rise Time, t
r
SCL, SDA Fall Time, t
f
Data Setup Time, t
SU;DAT
Data Hold Time, t
HD;DAT
NOTES
1
All voltages are measured with respect to GND, unless otherwise specified.
2
Typicals are at T = 25°C and represent most likely parametric norm. Shutdown current typ is measured with V
A
3
TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC, multiplexer and on-chip input attenuators, including an external series input
protection resistor value between zero and 1 kΩ.
Total monitoring cycle time is nominally m × 755 µs + n × 33244 µs, where m is the number of channels configured as analog inputs, plus two for the internal V
4
measurement and internal temperature sensor, and n is the number of channels configured as external temperature channels (D1 and D2).
5
The total fan count is based on two pulses per revolution of the fan tachometer output.
6
Open-drain digital outputs may have an external pull-up resistor connected to a voltage lower or higher than V
7
All logic inputs except ADD are tolerant of 5 V logic levels, even if V
8
Timing specifications are tested at logic levels of V
Specifications subject to change without notice.
SCL
t
HD:STA
SDA
t
BUF
P S
REV. A
Min
2.2
2.2
2.2
–1
1.3
600
600
1.3
0.6
100
is less than 5 V. ADD is a three-state input that may connected to V
CC
= 0.8 V for a falling edge and V
IL
t t
R F
t
LOW
t
HD:DAT
t
HIGH
Figure 1. Diagram for Serial Bus Timing
Typ Max Unit
V
0.8 V
500 mV
100 ns
V
0.8 V
V
µA
µA
1
20 pF
400 kHz
50 ns
µs
ns
ns
µs
µs
300 ns
µs
300
ns
900 ns
= 3.3 V.
CC
(up to 6.5 V absolute maximum).
CC
= 2.2 V for a rising edge.
IH
t
HD:STA
t
SU:STA
t
SU:DAT
S
–3–
ADM1024
Test Conditions/Comments
(See Note 7)
V = 2.85 V – 5.5 V
CC
V = 2.85 V – 5.5 V
CC
V = 2.85 V – 5.5 V
CC
V = V
IN CC
V = 0
IN
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
, GND, or left open-circuit.
CC
t
SU:STO
P
CC