Pentek 6230 Operating Manual page 6

Page 6
Table of Contents
Chapter 3: Memory Maps and Register Descriptions
3.10.4 GATE DISBL ..................................................................................................................... 54
3.10.5 GATE SRC ......................................................................................................................... 54
3.10.6 TRIG CLEAR ..................................................................................................................... 54
3.10.7 HOLD MODE ................................................................................................................... 55
3.10.8 GATE/TRIG ...................................................................................................................... 55
3.10.9 EXT GATE ......................................................................................................................... 55
3.11 Trigger Length Register..................................................................................................................... 56
Table 3−14: Trigger Length Register ............................................................................................. 56
3.12 Channel Control Register.................................................................................................................. 57
Table 3−15: Channel Control Register .......................................................................................... 57
3.12.1 RESET ................................................................................................................................. 57
3.12.2 DIV RST EN ...................................................................................................................... 57
3.12.3 FMTR EN ........................................................................................................................... 57
3.12.4 DAT MODEn .................................................................................................................... 58
3.13 Sync/Gate Generator Register ......................................................................................................... 59
Table 3−16: Sync/Gate Generator Register................................................................................... 59
3.13.1 FIFO GATE ........................................................................................................................ 59
3.13.2 SYNC .................................................................................................................................. 59
3.14 Interrupt Mask Register .................................................................................................................... 60
Table 3−17: Interrupt Mask Register............................................................................................. 60
Table 3−18: Interrupt Register Bits ................................................................................................ 61
3.15 Interrupt Flag Register ...................................................................................................................... 62
Table 3−19: Interrupt Flag Register ............................................................................................... 62
3.16 Interrupt Status Register ................................................................................................................... 63
Table 3−20: Interrupt Status Register............................................................................................ 63
3.17 Semaphore Register ........................................................................................................................... 64
Table 3−21: Semaphore Register .................................................................................................... 64
3.18 I/O Direction 2 Register (Model 6231 only)................................................................................... 65
Table 3−22: I/O Direction 2 Register (Model 6231 Option 102 only) ...................................... 65
3.19 I/O Data 2 Register (Model 6231 only)........................................................................................... 66
Table 3−23: I/O Data 2 Register (Model 6231 Option 102 only) ............................................... 66
3.20 I/O Direction Register....................................................................................................................... 67
Table 3−24: I/O Direction Register ................................................................................................ 67
3.21 I/O Enable Register ........................................................................................................................... 68
Table 3−25: I/O Enable Register ..................................................................................................... 68
3.21.1 I/O EN1 ............................................................................................................................. 68
3.21.2 I/O EN2 ............................................................................................................................. 68
3.22 I/O Data Register ............................................................................................................................... 69
Table 3−26: I/O Data Register ......................................................................................................... 69
3.23 Graychip 0 & 1 Registers ................................................................................................................... 70
Table 3−27: Graychip 0 & 1 Registers............................................................................................ 70
Table 3−28: Processor/Graychip Register Sets............................................................................. 70
Rev.: B.4
Pentek Mo d el 6230/6231 Oper a ting Ma nu al
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