Pentek 6230 Operating Manual page 19

Pentek Model 62 30/ 6231 O pera t ing M a nu a l
1.12 Specifications
Analog/Digital Converters
Quantity:
Device:
Sampling Rate:
Resolution:
Coupling:
Clock Source:
External Clock Input
Voltage Range:
Type:
Duty Cycle:
Frequency:
Impedance:
Sample Rate Control
Internal Clock:
External Clock:
Sample Rate Divider:
Gates
Quantity:
Polarity:
Routing:
Gate Disable:
Digital Receivers
Quantity:
Device:
Decimation:
Data Source:
Clock Source:
Sync:
Output:
Bypass Mode:
(continued)
Four [two] (enclosed in a shielded cover)
Analog Devices AD6644 (see
15 MHz to 65 MHz
14 bits
DC
Onboard crystal oscillator, external clock, or LVDS clock
(software selectable)
1 V (minimum), 5 V
P−P
Square or Sine Wave
45% to 55%
15 MHz to 65 MHz
50 Ω , AC coupled
64 MHz
15 MHz to 65 MHz
Divisible by 1, 2, or 4 (internal or external source)
Four [two], one per VIM baseboard BIFO
Programmable
Each VIM baseboard processor can create its own gate
Each gate can be disabled from its processor
(BIFO writes default to enable)
Eight [four] quad receiver chips (32 [16] receiver channels)
Graychip GC4016 (see
32 to 16,384
All A/D outputs are connected to each GC4016
A/D clock
Maskable inside each GC4016 chip
(All receiver channels directed to the same VIM base−
board BIFO must be synced at the GC4016 output)
Serial data
(Serial output rate must be same as input clock rate)
Data from the A/D converters can be written directly into the
VIM baseboard BIFOs (bypassing the GC4016s), at a sam−
ple rate equal to the A/D clock decimated by 1 or any
even value between 2 and 4096
Appendix B)
(maximum)
P−P
Appendix C)
Pa g e 1 9
Rev.: B.4