Pentek 6230 Operating Manual page 5

Pentek Model 62 30/ 6231 O pera t ing M a nu a l
Table of Contents
Chapter 3: Memory Maps and Register Descriptions
3.1 Overview..............................................................................................................................................41
3.2 Model 6230/6231 Memory Map.......................................................................................................41
Table 3−1: VIM Base Addresses for Models 4290 to 4295 VIM Baseboards ..........................41
Table 3−2: VIM Base Addresses for Model 4205 VIM Baseboards .........................................41
Table 3−3: Model 6230/6231 Memory Map ...................................................................................42
3.3 Virtex Config Register........................................................................................................................43
Table 3−4: Virtex Config Register ..................................................................................................43
3.3.1 WRITE ................................................................................................................................43
3.3.2 BUSY ...................................................................................................................................43
3.3.3 INIT .....................................................................................................................................43
3.3.4 DONE .................................................................................................................................44
3.3.5 PRGM .................................................................................................................................44
3.3.6 LD SRC ...............................................................................................................................44
3.4 Virtex Config Data Register ..............................................................................................................44
Table 3−5: Virtex Config Data Register.........................................................................................44
3.5 Wait States Register............................................................................................................................45
Table 3−6: Wait States Register.......................................................................................................45
3.6 Hardware Monitor Port Register......................................................................................................46
Table 3−7: Hardware Monitor Port Register ................................................................................46
Table 3−8: ADM1024 Registers .......................................................................................................47
3.7 Master Control Register.....................................................................................................................48
Table 3−9: Master Control Register................................................................................................48
3.7.1 RESET .................................................................................................................................48
3.7.2 SYNC SRC ..........................................................................................................................48
3.7.3 SYNC POL .........................................................................................................................49
3.7.4 EXT SYNC EN ...................................................................................................................49
3.7.5 MCLK DIVn .......................................................................................................................49
3.7.6 CLK SRC SEL ....................................................................................................................49
3.7.7 OSC DSBL ..........................................................................................................................49
3.7.8 EXT CLK ............................................................................................................................50
3.7.9 TERM ..................................................................................................................................50
3.7.10 MASTR ...............................................................................................................................50
3.8 Bypass Rate Divide Register .............................................................................................................51
Table 3−10: Bypass Rate Divide Register .....................................................................................51
3.9 Channel Enable Register....................................................................................................................52
Table 3−11: Channel Enable Register ............................................................................................52
Table 3−12: Register Bit Channel Assignments...........................................................................52
3.10 Gate Control Register.........................................................................................................................53
Table 3−13: Gate Control Register..................................................................................................53
3.10.1 INT EDGE x .......................................................................................................................53
3.10.2 GATE POL .........................................................................................................................54
3.10.3 GATE SELn ........................................................................................................................54
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Rev.: B.4