Pentek 6230 Operating Manual page 145

GC4016 MULTI-STANDARD QUAD DDC CHIP
ADDRESS 1: Status Register, Suggested default = 0x00
BIT TYPE NAME
0 LSB R/W READY
1 R/W MISSED
2 R/W RES_IOV
3 R/W RES_QOV
4 R/W CHECK_DONE
5-7 MSB R ZERO
The READY bit is used to tell an external processor when new output samples are ready to be read. If desired, the RDY pin
can be used as an interrupt to the external processor (See Section 3.8.1) to tell the processor when to read new samples. The
user does not need to set the READY bit if RDY is used. If READY is not set, however, the MISSED flag will not be valid.
ADDRESS 2: Page Register
BIT TYPE NAME
0 LSB R/W A3
1-7 MSB R/W PAGE[0:6]
In normal mode, the LSB is unused. PAGE is decoded to select the different control pages (see Table 12). Note that
addresses 0-7 are globally visible regardless of the PAGE value. Addresses 8-15 are unused. Addresses 16-31 are paged. In
the four bit address mode, the LSB provides address bit A3, effectively reducing each page to 8 words and doubling the number
of pages.
ADDRESS 3: Checksum Register
BIT TYPE NAME
0-7 R CHECKSUM[0:7]
The checksum register is a read only register which contains the checksum of the output data. The checksum is stored in
the checksum register and then starts over again each time the DIAG_SYNC (See address 4) occurs.
© GRAYCHIP,INC.
This document contains information which may be changed at any time without notice
DESCRIPTION
The user sets this bit after reading the output registers. The chip clears this bit
when new values have been loaded and it is time to read them.
The chip sets this bit If the user has not set the READY bit before the chip loads
the output registers. This bit high indicates that an error has occurred.
This control bit is set by the chip whenever the resampler I channel overflows.
The user can monitor this bit to see if the gain is too high. The user clears the bit
by writing a zero to it.
This control bit is set by the chip whenever the resampler Q channel overflows.
The user can monitor this bit to see if the gain is too high. The user clears the bit
by writing a zero to it.
This bit is set when the checksum sync is active (see DIAG_SYNC in address
4). The user can count sync cycles by clearing this bit and then waiting for it to
be set. The checksum will be complete after it this bit has been cleared and set
four times.
Reads back as zero.
DESCRIPTION
Used in the 4_BIT_ADDRESS mode (see global register 4) as address bit A3.
This bit is unused if 4_BIT_ADDRESS=0.
Page number for addressing different portions of the chip.
DESCRIPTION
The checksum.
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DATA SHEET REV 1.0
August 27, 2001