Pentek 6230 Operating Manual page 154

GC4016 MULTI-STANDARD QUAD DDC CHIP
ADDRESS 28: Peak Control, Suggested default = 0x1D
BIT TYPE
0-2 LSB R/W
3-4 R/W
5 R/W
6-7 R/W
ADDRESS 29: Peak Count, Read only
BIT TYPE
0-7 R
ADDRESS 30: Fine Gain Byte 0, Suggested default = 0x00
BIT TYPE
0-7 R/W
ADDRESS 31: Fine Gain Byte 1, Suggested default = 0x00
BIT TYPE
0-5 R/W
6-7 MSB R/W
The fine gain control can apply a gain of FINE_GAIN/1024 providing a range of 0 to almost 16. Double buffering and
synchronization for data transfer is provided to allow the user to change the gain dynamically without causing glitches in the signal
(See GAIN_SYNC in address 22). This also allows the user to synchronously change gain in multiple channels even across
different chips.
© GRAYCHIP,INC.
This document contains information which may be changed at any time without notice
NAME DESCRIPTION
PEAK_SYNC Synchronizes the peak counter circuitry using the mode selected in Table 7.
When the selected sync occurs, the counter transfers its contains to a read only
control register and clears the counter.
PEAK_THRESHOLD When the input peak detect mode is selected (PEAK_MODE=0), the input word
is checked against a threshold. The threshold values are 1/4, 1/2, 3/4, or 4/4 (full
scale) for PEAK_THRESH= 0,1,2, or 3 respectively. The absolute value of the
top 11 bits is compared to the selected threshold. This is only used when the
PEAK_MODE is zero.
PEAK_MODE If PEAK_MODE is zero, the input word is selected as the source to the peak
counter, otherwise one of three overflow bits (see PEAK_SELECT at address
26) is monitored by the peak counter.
Unused
NAME DESCRIPTION
PEAK_COUNT Count of number of overflows or samples above threshold during last sync
period. The counter hard-limits at 255.
NAME DESCRIPTION
FINE_GAIN[0:7] The LSBs of the fine gain control
NAME DESCRIPTION
FINE_GAIN[8:13] The MSBs of the fine gain control
Unused
- 41 -
DATA SHEET REV 1.0
August 27, 2001