Pentek 6230 Operating Manual page 160

GC4016 MULTI-STANDARD QUAD DDC CHIP
ADDRESS 17: Output Format, Suggested default = 0x40
BIT TYPE
0 (LSB) R/W
1 R/W
2 R/W
3 R/W
4 R/W
5-7 (MSB) R/W
ADDRESS 18: Output Mode Cleared on powerup., Suggested default = (see Table 3)
BIT TYPE
0 (LSB) R/W
1 R/W
2 R/W
3 R/W
4 R/W
5-6 R/W
7 (MSB) R/W
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This document contains information which may be changed at any time without notice
NAME DESCRIPTION
INV_SCK Invert SCK output. The serial, nibble, link and parallel outputs normally change
on the rising edge of SCK. If INV_SCK is set high the clock is inverted so data
changes on the falling edge.
INV_RDY Invert RDY output. RDY is normally active high. This control bit is used for uP
and parallel modes. It has no effect in serial, LINK, or nibble modes.
INV_SFS Invert SFS output. SFS is normally active high.
TAG_EN Enable tags. The four bit tags replace the four LSBs of the data when TAG_EN
is set. The BITS_PER_WORD (address 20) control determines the tag location.
RDY_WIDTH The RDY pulse is 4 (RDY_WIDTH=0) or 16 (RDY_WIDTH=1) CK cycles. Valid
for the uP mode only, must be set to 0 for all other modes.
OUT_BLK_SYNC Output circuit sync source. See table 7 for the sync modes.
The OUT_BLK_SYNC is used to synchronize the output timing among multiple
GC4016 chips. The OUT_BLK_SYNC should only be made active during
initialization. Use during operation may cause unknown output transients.
NAME DESCRIPTION
LINK Enable LINK protocol. This mode supports Analog Devices LINK protocol. In
this mode the RDY pin serves as LINK Acknowledge and is an input to the
GC4016 (EN_RDY must be low). NIBBLE must also be set high (eight bit LINK
mode is not supported) and OUTPUT_MODE must be set to 2. The PARALLEL
control bit must be low.
NIBBLE Enable nibble mode. This mode is similar to serial except the four pins P0-3
output one nibble at a time. TDM of several chips is supported with one acting
as the master (EN_RDY=MASTER=1) and the others as the slave
(EN_RDY=MASTER=0).
PARALLEL Enable parallel mode.
MASTER Normally set high. Is set low by slave chips in TDM serial or nibble modes. The
RDY pin is an output when MASTER=1, and is an input when MASTER=0.
REAL_ONLY Normally set low. Is set high when outputting real, instead of complex, data.
Normally used with the complex to real modes of the PFIR (see Section 3.3.7).
OUTPUT_MODE The output mode selection is:
Note that only one mode is supported at a time.
REVERSE_IQ Used when OUTPUT_ORDER=0 to swap I and Q. This is useful for link or
nibble mode outputs when packing two 16 bit words into a 32 bit transfer. See
Section 3.8.5.
0 for microprocessor mode,
1 for serial mode,
2 for nibble or LINK modes, or
3 for parallel mode.
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DATA SHEET REV 1.0
August 27, 2001