Pentek 6230 Operating Manual page 162

GC4016 MULTI-STANDARD QUAD DDC CHIP
ADDRESS 20: Output Word Sizes, Suggested default = (see Table 3)
BIT TYPE
0-2 (LSB) R/W
3-5 R/W
6-7 (MSB) R/W
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This document contains information which may be changed at any time without notice
NAME DESCRIPTION
WORDS_PER_FRAME Serial, nibble and parallel modes:
Serial or nibble TDM modes:
Link mode:
Microprocessor mode:
BITS_PER_WORD Sets the number of bits per word in the serial, nibble and link modes and
determines the location of tag bits in all modes.
Serial mode:
Nibble and link modes:
Parallel or microprocessor modes:
Note that rounding is independent and is controlled by the ROUND control in
address 19 of the resampler control page.
BLOCK_SIZE Outputs are transferred from the resampler to the output in blocks of size
(BLOCK_SIZE+1) complex samples (two words per sample). Values 0,1, and 3
are valid. Value 2 is mapped to be the same as 3.
Synchronous serial, nibble and parallel modes:
Link mode and asynchronous serial, nibble and parallel modes:
Microprocessor mode:
The number of output words (not complex pairs) in a frame is
(WORDS_PER_FRAME+1). This value should be less than or equal to the
frame length. It should also be less than or equal to the number of output
channels.
(WORDS_PER_FRAME+1) is the number of words THIS chip inserts into
the TDM stream.
In the link mode only 32 bit transfers are understood. A single 32 bit word is
transferred by setting WORDS_PER_FRAME to 0 and BITS_PER_WORD
to 1. Two 16 bit words packed together in a single 32 bit transfer is done by
setting WORDS_PER_FRAME to 1 and BITS_PER_WORD to 0.
Unused, set to 0.
For serial outputs the number of bits per serial word is set as
4*(BITS_PER_WORD+1), where BITS_PER_WORD ranges from 2 to 7.
Values 2-5 create 12-24 bit serial outputs with tags (if enabled) in the least
significant nibble. Values 6 and 7 create 28 and 32 bit outputs respectively
with the last one or two nibbles zeros and tags in the sixth nibble.
For nibble and link modes the number of bits per word are 16 for
BITS_PER_WORD=0 and 32 for BITS_PER_WORD=1. Tag bits replace
the least significant nibble when BITS_PER_WORD=0, and replace the
sixth nibble when BITS_PER_WORD=1. The least significant two nibbles
are always zero when BITS_PER_WORD=1.
For parallel or uP outputs BITS_PER_WORD only affects the placement of
the tag bits. The least significant four bits of the 4*(BITS_PER_WORD+1)
bits are replaced. BITS_PER_WORD ranges from 2 to 5 in these modes.
For synchronous serial, nibble and parallel outputs the block size will
typically match the number of output channels.
For link and asynchronous outputs the block size should be minimum
(BLOCK_SIZE=0).
For the microprocessor modes the BLOCK_SIZE should be 3 which will
minimize the interrupt rate to one interrupt per 4 samples (real or complex).
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DATA SHEET REV 1.0
August 27, 2001