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GC4016 REGISTER ASSIGNMENT QUICK REFERENCE GUIDE
Page
Address
Name
R
32-63
16-31
Filter Taps
E
64
16 (0x10)
N-Channels
S
(0x40)
A
17 (0x11)
N-Multiplies
M
18 (0x12)
Filter Select
P
L
19 (0x13)
Final Shift
E
20 (0x14)
Channel Map
R
21 (0x15)
Add To
22 (0x16)
Clock Divide
23 (0x17)
Ratio Map
65
16-19
Res Ratio 0
(0x41)
20-23
Res Ratio 1
24-27
Res Ratio 2
28-31
Res Ratio 3
96,97
16-31
Output Data
O
98
16 (0x10)
Tristate Controls
U
(0x62)
17 (0x11)
Output Format
T
P
18 (0x12)
Output Mode
U
19 (0x13)
Frame Control
T
20 (0x14)
Word Sizes
21 (0x15)
Clock Control
22 (0x16)
Serial Mux
23 (0x17)
Output Tag A
24 (0x18)
Output Tag B
25 (0x19)
Output Tag C
26 (0x1A) Output Tag D
27 (0x1B) Revision
28 (0x1C) Miscellaneous
.
Global Syncs (Addresses 4 and 5)
Sync
Value
DIAG_SYNC
7 (always)
OUTPUT_SYNC
4 (OS)
COUNTER_SYNC
4 (OS)
Outout Circuit Sync (Page 98)
OUT_BLK_SYNC
2 (SIA)
Resampler syncs (Page 64)
RES_SYNC
2 (SIA)
RATIO_SYNC
7(always)
(
GAIN
=
---------------------
NZEROS 1
REV 1.0
7(MSB)
6
Resampler Coefficients, 8 LSBs in even addresses, 4 MSBs in odd addresses. (Must be loaded in the blocks 16-23 and 24-31)
-
-
NO_SYM_RES
FILTER_SEL_3
-
TAG_22
CHAN_MAP_D
-
RES_CLK_DIV (The resampler clock rate is 2*F
RATIO_MAP_3
RATIO_0, Resampler ratio 0. RATIO = 2
RATIO_1, Resampler ratio 1.
RATIO_2, Resampler ratio 2.
RATIO_3, Resampler ratio 3.
See Tables 4,5, and 6 for details
EN_PAR
EN_P3
OUT_BLK_SYNC
REVERSE_IQ
OUTPUT_MODE
SFS_MODE
BLOCK_SIZE
OUTPUT_ORDER
SMUX_3
Description
Only used during diagnostics
The SO output is used during initialization
Sync counter with one shot pulse
Sync the output block during initialization
Sync the Resampler during initialization
Set to always except when synchronously
changing ratios
(
×
5
)N
SHIFT SCALE
+
+
6
BIG_SCALE
1
2
+
5
4
RES_SYNC
FILTER_SEL_2
ROUND (12B,16B, 20B,24B)
CHAN_MAP_C
RATIO_SYNC
/(RES_CLK_DIV+1))
CK
RATIO_MAP_2
26
(Resampler input sample rate)/(Resampler output sample rate)
EN_P2
EN_P1
RDY_WIDTH
REAL_ONLY
BITS_PER_WORD
NSERIAL
SMUX_2
TAG_AQ
TAG_BQ
TAG_CQ
TAG_DQ
Mask Revision Number
-
Channel Syncs (Pages 7, 15, 23 and 31)
Sync
PHASE_SYNC
FREQ_SYNC
NCO_SYNC
DITHER_SYNC
ZPAD_SYNC
DEC_SYNC
FLUSH_SYNC
GAIN_SYNC
PEAK_SYNC
)
–
62
(
COARSE
)
(
CFIR_SUM
2
-------------------
65536
3
2
NF=(NFILTER-1)
NM=(NMULT-1)
FILTER_SEL_1
FINAL_SHIFT
CHAN_MAP_B
(must be 0)
ADD_C_TO_D
ADD_B_TO_C
RATIO_MAP_1
EN_P0
EN_SFS
EN_RDY
TAG_EN
INV_SFS
INV_RDY
MASTER
PARALLEL
NIBBLE
FRAME_LENGTH
WORDS_PER_FRAME
SCK_RATE
SMUX_1
TAG_AI
TAG_BI
TAG_CI
TAG_DI
EN_SO
Value
Description
7 (always)
Use phase settings as they are loaded
7 (always)
Use frequency settings as they are loaded
2 (SIA)
Sync the phase accumulator during
initialization. Set to SIB for frequncy hopping.
0 (never)
Can free run except during diagnostics, or
or 2 (SIA)
reset during initialization
2 (SIA)
Sync the zero pad circuit during initialization
2 (SIA)
Sync the channel decimation during
initialization
2 (SIA)
Flush the channels during initialization
7 (always)
Use fine gain settings as they are loaded
5 (TC)
Periodically capture peak count data
)
(
)
(
)
(
PFIR_SUM
FINE_GAIN
RES_SUM
------------------ -
--------------------
--------------------------------------------- -
×
65536
1024
32768 NDELAY
Suggested
1
0(LSB)
Default
Bypass
NC =(NCHAN-1)
23
46
FILTER_SEL_0
00
35
CHAN_MAP_A
E4
ADD_A_TO_B
70
00
RATIO_MAP_0
00
04000000
04000000
04000000
04000000
EN_SCK
See Table 3
INV_SCK
LINK
SMUX_0
10
32
54
76
read only
EN_4_FS
02
) 2
(
FINAL_SHIFT
)
August 27, 2001
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