Pentek 6210 Operating Manual page 98

CONTROL WORD 9: AGC CONFIGURATION 2 (SYNCHRONIZED TO PROCCLK)
BIT
POSITION FUNCTION
31-28 Reserved
27-16 Upper Limit
15-12 Reserved
11-0 Lower Limit
CONTROL WORD 10: AGC SAMPLE GAIN CONTROL STROBE (SYNCHRONIZED TO PROCCLK)
BIT
POSITION FUNCTION
N/A Sample AGC Gain
Level
CONTROL WORD 11: TIMING NCO CONFIGURATION (SYNCHRONIZED TO PROCCLK)
BIT
POSITION FUNCTION
31-6 Reserved
5 Enable External
Timing NCO Sync
4-3 Number of Offset Fre-
quency Bits
2 Enable Offset
Frequency
1 Clear Phase
Accumulator
0 Timing NCO Phase
Accumulator Load On
Update
CONTROL WORD 12: TIMING NCO CENTER FREQUENCY (SYNCHRONIZED TO PROCCLK)
BIT
POSITION FUNCTION
31-0 Timing NCO Center
Frequency
3-50
HSP50214B
Reserved.
Maximum Gain/Minimum Signal. The upper four bits are used for exponent; the remaining bits form the
mantissa in the fractional offset binary: [eeeemmmmmmmm]. See the AGC Section for details. Bit 27 is
the MSB. The gain is in dB. G = (6.02)(eeee) + 20log
GAIN dB/20
eeee = Floor [log (10
2
mmmmmmmm = Floor [256(10
Reserved.
Minimum Gain/Maximum Signal. The upper four bits are used for exponent; the remaining bits form the
mantissa in the fractional offset binary: [eeeemmmmmmmm]. See the AGC Section for details. Bit 11 is
the MSB. The gain is in dB. G = (6.02)(eeee) + 20log
GAIN dB/20
eeee = Floor [log (10
2
mmmmmmmm = Floor [256(10
Writing to this location samples the output of the AGC loop filter to stabilize the value for µP reading.
Reserved.
0- SYNCIN2 has no effect on the timing NCO.
1- When SYNCIN2 is asserted, the timing NCO center frequency and phase are updated with the value
loaded in their holding registers. If bit 0 of this word is set to 1, the phase accumulator feedback is also
zeroed.
00 - 8 bits.
01 - 16.
10 - 24.
11 - 32.
0- Zero Offset Frequency to Adder.
1- Enable Offset Frequency.
0- Enable Accumulator.
1- Zero Feedback in Accumulator.
When this bit is set to 1, the µP update to the timing NCO frequency or an external timing NCO load
using SYNCIN2 will zero the feedback of the phase accumulator as well as update the phase and fre-
quency. This function can be used to set the NCO to a known phase synchronized to an external event.
These bits control the frequency of the timing NCO. The frequency range of the NCO is from 0 to F
where F is the input sample rate to the resampling filter. The bits are computed by the
SAMP RESAMP
equation: N =(f /F
OUT RESAMP
a transfer to the Active Register is done by writing to Control Word 14 or by generating a SYNCIN2 with
Control Word 11, Bit 5 set to 1.
DESCRIPTION
(1.0 + 0.mmmmmmmm)
10
)]
GAIN dB/20 eeee
/2 - 1)]
(1.0 + 0.mmmmmmmm)
10
)]
GAIN dB/20 eeee
/2 - 1)]
DESCRIPTION
DESCRIPTION
DESCRIPTION
32
)*2 . Bit 31 is the MSB. This location is a holding register. After loading,
RE-