Pentek 6210 Operating Manual page 83

I (15:0)
(2's COMP)
Q (15:0)
(2's COMP)
|r| (15:0)
(O; UNSIGNED BINARY)
φ (15:0)
(2's COMP)
f
(15:0)
(2's COMP)
TE
(15:0)
(2's COMP)
AGC
(15:0)
(O; UNSIGNED BINARY)
ZERO
PROCCLK
NUM OF SER WORD LINKS IN A CHAIN
SERIAL OUT CLOCK DIVIDER
SERIAL OUTPUT SYNC POSITION
SERIAL OUTPUT CLOCK POLARITY
SERIAL OUTPUT SYNC POLARITY
† Controlled via microprocessor interface
‡
Polarity is programmable
AGC DATA SERIAL OUTPUT TAG BIT
TIMING ERROR DATA SERIAL OUTPUT TAG BIT
FREQUENCY DATA SERIAL OUTPUT TAG BIT
PHASE DATA SERIAL OUTPUT TAG BIT
MAGNITUDE DATA SERIAL OUTPUT TAG BIT
Q DATA SERIAL OUTPUT TAG BIT
I DATA SERIAL OUTPUT TAG BIT
SHIFT REG
SHIFT REG
SHIFT REG
SHIFT REG
SHIFT REG
SHIFT REG
SHIFT REG
SHIFT REG
MUX
SEROUTB
SOURCE
PROGRAMMABLE
DIVIDER
†
†
†
†
†
FIGURE 34. SERIAL OUTPUT FORMATTER BLOCK DIAGRAM
3-35
HSP50214B
†
†
†
†
†
†
†
DATA SOURCE FOR SEROUTA
LINK FOLLOWING I DATA
LINK FOLLOWING Q DATA
LINK FOLLOWING MAG DATA
LINK FOLLOWING PHASE DATA
LINK FOLLOWING FREQ DATA
LINK FOLLOWING TIMING DATA
LINK FOLLOWING AGC DATA
FOLLOWS I
SHIFT REG
FOLLOWS Q
SHIFT REG
FOLLOWS |r|
CROSS
SHIFT REG
MATRIX
SWITCH FOLLOWS φ
CROSS
SHIFT REG
MATRIX
SWITCH
FOLLOWS
SHIFT REG
FOLLOWS TE
SHIFT REG
FOLLOWS AGC
SHIFT REG
SEROUTA
SOURCE
†
DATA SOURCE FOR SEROUTB
XXX SOURCE
000 I
†
001 Q
†
010 MAG
†
011 PHASE
†
† 100 FREQUENCY
†
101 TIMING ERROR
†
110 AGC
†
111 ZERO
f
6 5 4 3
SERIAL OUTPUT SHIFT REGISTER
6 5 4 3
SERIAL OUTPUT SHIFT REGISTER
2 1 0
SEROUTA
2 1 0
SEROUTB
‡
SERCLK
‡
SERSYNC